843004I RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 20
Technical content
Features
- Four 3.3V differential LVPECL output pairs
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input
- Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
- VCO range: 560MHz – 680MHz
- Output skew: 50ps (maximum)
- RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (2.55MHz – 20MHz): 0.47ps (typical)
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Bank A Frequency Table Inputs N Div. Value M/N Div. Value Output Frequency (MHz)Input Frequency (MHz) F_SEL1 F_SEL0 M Div. Value 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 26.04166 0 1 24 4 6 156.25 23.4375 0 0 24 3 8 187.5 Pin Assignment 843004I 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View nQ1 VCCO nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 nQ2 VCCO VEE nQ3 nc nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT Phase Detector VCO 637.5MHz (w/26.5625MHz Reference) M = 24 (fixed) F_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 OSC nQ0 nQ1 nQ2 nQ3 nPLL_SEL nXTAL_SEL XTAL_IN XTAL_OUT TEST_CLK MR F_SEL[1:0] Pulldown Pulldown Pulldown Pulldown Pulldown 26.5625MHz Block Diagram
Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 V CCO Power Output supply pins. 4, 5 Q0, nQ0 Output Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. 9V CCA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 11 V CC Power Core supply pin. 15, 19 V EE Power Negative supply pins. 16 TEST_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. reference source. When HIGH, selects TEST_CLK. When LOW, selects XTAL. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels.
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VCC = VCCA = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 70C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 130 mA ICCA Analog Supply Current Included in I EE 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 120 mA ICCA Analog Supply Current Included in I EE 12 mA
NOTE 1: Outputs termination with 50 to VCCO – 2V. Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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Table 5A. AC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Table 5B. AC Characteristics, VCC = VCCA = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typic al Maximum Units fOUT Output Frequency Range F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 212.5MHz, (2.55MHz – 20MHz) 0.47 ps 159.375MHz, (1.875MHz – 20MHz) 0.52 ps 156.25MHz, (1.875MHz – 20MHz) 0.52 ps 106.25MHz, (637kHz – 5MHz) 0.62 ps 53.125MHz, (637kHz – 50MHz) 0.67 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency Range F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random) 212.5MHz, (2.55MHz – 20MHz) 0.49 ps 159.375MHz, (1.875MHz – 20MHz) 0.52 ps 156.25MHz, (1.875MHz – 20MHz) 0.52 ps 106.25MHz, (637kHz – 5MHz) 0.65 ps 53.125MHz, (637kHz – 50MHz) 0.71 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle
Rev B 12/9/14 6 FEMTOCLOCK® LVCMOS /CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843004I DATA SHEET Typical Phase Noise at 53.125MHz at 3.3V Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 53.125MHz RMS Phase Jitter (Random) 637kHz to 5MHz = 0.49ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 212.5MHz at 3.3V Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 212.5MHz RMS Phase Jitter (Random) 2.55MHz to 20MHz = 0.47ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
Rev B 12/9/14 8 FEMTOCLOCK® LVCMOS /CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843004I DATA SHEET Parameter Measurement Information 3.3V Core/ 3.3V Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V Core/ 2.5V Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -1.3V ± 0.165V VCCA, VCCO nQx Qx nQy Qy nQ[0:3] Q[0:3] SCOPE Qx nQx VEE VCC, -0.5V ± 0.125V VCCA, VCCO Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ[0:3] Q[0:3]
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. Figure 1. Power Supply Filtering resistor can be tied from the TEST_CLK to ground. should either be left floating or terminated.
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
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Figure 6. 843004I Schematic Example
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This section provides information on power dissipation and junction temperature for the 843004I. Equations and example calculations are also provided. The total power dissipation for the 843004I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
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- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP
FEMTOCLOCK® LVCMOS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev B 12/9/14 18 FEMTOCLOCK® LVCM OS/CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843004I DATA SHEET Revision History Sheet Rev Table Page Description of Change Date A T5A, T5B AC Characteristics Table - added Thermal Note. Added Recommendations for Unused Input and Output Pins section. Reworded text in Power Supply Filtering Techniques. Added Overdriving the XTAL Interface section. Updated Figures 4A and 4B. Ordering Information Table - added lead-free marking. Deleted “ICS” prefix from part/order number. Datasheet conversion. 2/19/10
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