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FemtoClock® Crystal/LVCMOS-to- 3.3V LVPECL Frequency Synthesizer 843004I-04 DATASHEET 843004I-04 REVISION A 5/27/15 1 ©2015 Integrated Device Technology, Inc. Phase Detector VCO M = ÷32 OSC ÷1 0 GENERAL DESCRIPTION The 843004I-04 is a 4 output LVPECL Synthesizer optimized to generate clock frequencies for a variety of high performance applications. This device can select its input reference clock from either a crystal input or a single-ended clock signal. It can be confi gured to generate 4 outputs with individually selectable divide-by-one or divide-by-four function via the 4 frequency select pins (F_SEL[3:0]). The 843004I-04 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter. This ensures that it will easily meet clocking requirements for SDH (STM-1/STM-4/STM- 16) and SONET (OC-3/OC12/OC-48). This device is suitable for multi-rate and multiple port line card applications. The 843004I- 04 is conveniently packaged in a small 24-pin TSSOP package.
FEATURES
Four LVPECL outputs Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Supports the following applications: SONET/SDH, SATA, or 10Gb Ethernet Output frequency range: 140MHz - 170MHz, 560MHz - 680MHz VCO range: 560MHz - 680MHz Crystal oscillator and CLK range: 17.5MHz - 21.25MHz RMS phase jitter @ 622.08MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.82ps (typical) RMS phase jitter @ 156.25MHz output, using a 19.53125MHz crystal (1.875MHz - 20MHz): 0.57ps (typical) RMS phase jitter @ 155.52MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.94ps (typical) Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in lead-free RoHS compliant package PIN ASSIGNMENT 843004I-04 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View nQ1 VCCo nQ0 MR F_SEL3 nc VCCA F_SEL0 VCC F_SEL1 nQ2 V CCO nQ3 VEE F_SEL2 INPUT_SEL CLK V EE XTAL_IN XTAL_OUT BLOCK DIAGRAM CLK INPUT_SEL MR F_SEL0 F_SEL1 F_SEL2 F_SEL3 nQ0 nQ1 nQ2 nQ3 Pulldown Pulldown Pulldown Pullup Pullup Pullup Pullup XTAL_IN XTAL_OUT
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TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE
10 Gigabit Ethernet
1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 V CCO Power Output supply pins. 4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
abled. LVCMOS/LVTTL interface levels. Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3. CCA Power Analog supply pin. 11 V CC Power Core supply pin. 15, 19 V EE Power Negative supply pins. 16 CLK Input Pulldown LVCMOS/LVTTL clock input.
17 INPUT_SEL Input Pulldown
Selects between crystal or CLK inputs as the the PLL Reference source. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels. Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
3 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 mA ICCA Analog Supply Current 10 mA ICCO Output Supply Current 120 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK, MR, INPUT_SEL VCC = VIN = 3.465 150 µA F_SEL0:F_SEL3 V CC = VIN = 3.465 5 µA IIL Input Low Current CLK, MR, INPUT_SEL VCC = 3.465V, VIN = 0V -5 µA F_SEL0:F_SEL3 V CC = 3.465V, VIN = 0V -150 µA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 70°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CCO - 1.4 V CCO - 0.9 V VOL Output Low Voltage; NOTE 1 V CCO - 2.0 V CCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
4 REVISION A 5/27/15
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Output skew measurements taken with all outputs in the same divide confi guration. NOTE 4: Please refer to the Phase Noise Plot.
5 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER 843004I-04 DATA SHEET
6 REVISION A 5/27/15
The 843004I-04 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843004I-04 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01 μF bypass capacitor should be connected to each V CCA. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING Figure 2. CRYSTAL INPUt INTERFACE
7 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE can also be accomplished by removing R1 and making R2 50Ω. tied from XTAL_IN to ground. 1kΩ resistor can be tied from the CLK input to ground. protection. A 1kΩ resistor can be used. output pair should either be left fl oating or terminated.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER 843004I-04 DATA SHEET
8 REVISION A 5/27/15
TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
9 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
FIGURE 5. ICS844004I-04 SCHEMATIC EXAMPLE
10 REVISION A 5/27/15
TABLE 7. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION This section provides information on power dissipation and junction temperature for the 843004I-04. Equations and example calculations are also provided. The total power dissipation for the 843004I-04 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW
- Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.465V, with all outputs switching) = 415.8 + 120mW = 535.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming an air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.536W * 65°C/W = 119.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 65°C/W 62°C/W
11 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 6. termination voltage of VCC- 2V. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
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TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
13 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
TABLE 9. PACKAGE DIMENSIONS
14 REVISION A 5/27/15
TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
15 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Description of Change Date A T10 14 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/26/10 A T10 14 Updated data sheet format. Ordering Information - Removed leaded devices. 5/17/15
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