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Technical content

Features

  • Four 3.3V differential LVPECL output pairs
  • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input
  • Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
  • VCO range: 560MHz – 680MHz
  • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.54ps (typical)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) package Frequency Select Function Table Inputs Output Frequency (MHz) (25MHz Reference)F_SEL1 F_SEL0 M Div. Value N Div. Value M/N Div. Value 0 0 25 4 6.25 156.25 01 2 5 5 5 1 2 5 1 0 25 10 2.5 62.5 1 1 25 Not Used Not Used Pin Assignment 843004I-01 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View nQ1 VCCO nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 nQ2 VCCO VEE nQ3 VCC nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT Phase Detector VCO 625MHz (w/25MHz Reference) OSC M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used nQ0 nQ1 F_SEL[1:0] nPLL_SEL nXTAL_SEL MR TEST_CLK XTAL_IN XTAL_OUT Pulldown Pulldown Pulldown Pulldown Pulldown nQ2 nQ3 Block Diagram FemtoClock® Crystal-to-3.3V, 2.5V LVPECL Frequency Synthesizer 843004I-01

Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 V CCO Power Output supply pins. 4, 5 Q0, nQ0 Output Differential output pair. LVPECL interface levels.

6 MR Input Pulldown

clock (PLL Bypass). LVCMOS/LVTTL interface levels. 9V CCA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 11, 18 V CC Power Core supply pins. XTAL_IN Input Parallel resonant crystal interface. XT AL_OUT is the output, XTAL_IN is the input. 15, 19 V EE Power Negative supply pins. 16 TEST_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. inputs. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels.

3©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 70C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 130 mA ICCA Analog Supply Current Included in I EE 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 120 mA ICCA Analog Supply Current Included in I EE 12 mA

NOTE 1: Outputs termination with 50 to VCCO – 2V. NOTE 1: Outputs termination with 50 to VCCO – 2V. Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

5©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Table 5A. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Table 5B. AC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency Range F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.54 ps 125MHz, (1.875MHz – 20MHz) 0.58 ps 62.5MHz, (637kHz – 10MHz) 0.70 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency Range F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.54 ps 125MHz, (1.875MHz – 20MHz) 0.58 ps 62.5MHz, (637kHz – 10MHz) 0.74 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 %

6©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Typical Phase Noise at 156.25MHz (3.3V) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.54ps (typical) Noise Power dBc Offset Frequency (Hz)

7©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Typical Phase Noise at 62.5MHz (3.3V) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.70ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

8©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -1.3V ± 0.165V VCCA, VCCO nQx Qx nQy Qy nQ0:nQ3 Q0:Q3 SCOPE Qx nQx VEE VCC, -0.5V ± 0.125V VCCO VCCA, Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQ0:nQ3 Q0:Q3

9©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843004I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. Figure 1. Power Supply Filtering resistor can be tied from the TEST_CLK to ground. should either be left floating or terminated. chosen to minimize the ppm error.

11©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

This section provides information on power dissipation and junction temperature for the 843004I-01. Equations and example calculations are also provided. The total power dissipation for the 843004I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP

17©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet

Ordering Information

Table 9. Ordering Information

18©2016 Integrated Device Technology, Inc January 18, 2016 843004I-01 Data Sheet Revision History Sheet Rev Table Page Description of Change Date B T3E Added 2.5V LVPECL DC Characteristics Table. Added LVCMOS to XTAL Interface section. Ordering Information Table - added Lead-Free marking. 4/22/09 B T3D, T3E Pin Description Table - revised pin 7 description. LVPECL Tables - corrected VOH/VOL Parameter rows from current to voltage and corrected units from µA to V. LVCMOS to XTAL Interface section - added sentence to end. Power Considerations, 2. Junction Temperature - reworded sentence. Ordering Information Table - corrected Temperature column from -30 to -40. Updated header/footer of datasheet. 8/11/09 B6 156.25MHz Phase Noise Plot - corrected filter from Fibre Channel to 10Gb Ethernet and corrected typo 1.875MHz from 1.875MkHz. 1/26/10 B T9 Updated Overdriving the XTAL Interface application note. Ordering Information Table - corrected LF marking. 3/24/11 B T9 17 Removed leaded orderable parts from the Ordering Information table. 11/14/12 B T9 17 Removed ICS from part the part number where needed. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Updated header and footer. 1/18/16

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