ICS843004I-156 IDT | Alldatasheet
Document overview
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Technical content
Features
- Four 3.3V differential LVPECL output pairs
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input
- 156.25MHz output frequency
- VCO range: 560MHz – 680MHz
- RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.49ps (typical)
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Pin Assignment ICS843004I-156 24-Lead TSSOP, E-Pad 4.4mm x 7.8mm x 0.925mm package body G Package Top View nQ1 VCCO nQ0 MR nPLL_SEL nc VCCA nc VCC nc nQ2 VCCO VEE nQ3 VCC nXTAL_SEL REF_CLK VEE XTAL_IN XTAL_OUT 1 1 Phase Detector VCO 625MHz (w/25MHz Reference) OSC M = 25 (fixed) nQ0 nQ1 nQ1 nQ2 nQ3 nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR Pulldown Pulldown Pulldown Pulldown 25MHz Block Diagram
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 2 ©2013 Integrated Device Technology, Inc. Table 1. Pin Descriptions Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ1, Q1 Output Differential ou tput pair. LVPECL interface levels. 3, 22 V CCO Power Output supply pins. 4, 5 Q0, nQ0 Output Differential ou tput pair. LVPECL interface levels.
6 MR Input Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. selects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 8, 10,12 nc Unused No connect. 9V CCA Power Analog supply pin. 11, 18 V CC Power Core supply pins. 15, 19 V EE Power Negative supply pins. 16 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. XTAL inputs. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential ou tput pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential ou tput pair. LVPECL interface levels.
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 3 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 32.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.13 3.3 V CC V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 mA ICCA Analog Supply Current Included in I EE 13 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage VCC – 0.12 2.5 V CC V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 110 mA ICCA Analog Supply Current Included in I EE 12 mA
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 4 ©2013 Integrated Device Technology, Inc. NOTE 1: Outputs termination with 50 to VCCO – 2V. NOTE 1: Outputs termination with 50 to VCCO – 2V. Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 5 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Table 5A. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Table 5B. AC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency Range 156.25 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.49 ps tR / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency Range 156.25 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.49 ps tR / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 %
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 6 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 156.25MHz (3.3V) Typical Phase Noise at 156.25MHz (2.5V) 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.49ps (typical) Noise Power dBc Hz Offset Frequency (Hz) 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.49ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 7 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -1.3V ¬± 0.165 VCCA VCCO tsk(o) nQx Qx nQy Qy tPW tPERIOD tPW tPERIOD odc = x 100% nQ0:nQ3 Q0:Q3 SCOPE Qx nQx VEE VCC, -0.5V ¬± 0.125 VCCO VCCA Offset Frequencyf1 f2 Phase Noise Plot Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter = Noise Power 2 * * ƒ 1 * 20% 80% 80% 20% tR tF VSWING nQ0:nQ3 Q0:Q3
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 9 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK Input For applications not requiring the use of a reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50LVPECL Input 3.3V 3.3V
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 12 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Schematic Example Figure 5 (next page) shows an example of ICS843004I-156 application schematic in which the device is operated at VCC = +3.3V. The schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. For example MR, nPLL_SEL and nXTAL_SEL can be configured from an FPGA instead of pull up and pull down resistors as shown. There are three PECL termination options shown as examples of valid LVPECL terminations. 1. The simple three resistor termination of R5, R6 and R7 is easiest to layout and lowest power. 2. The standard four resistor LVPECL termination that explicitly realizes the VCC - 2V VTT termination voltage as a Thevinin equivalent. It is however higher power than the three resistor termination. 3. An AC termination, used when coupling the ICS843004I-156 LVPECL output stage to a different logic family receiver. Note that in the AC termination the pull down resistors R8 and R9 that bias the LVPECL output stage are to be placed on the ICS843004I-156 side of the PCB directly adjacent to pins 21 and 20 for best signal integrity. This device package has an ePAD that is connected to ground internally. The ePAD is to be connected to VEE/GND through vias in order to improve heat dissipation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the VCC pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor on the VCC pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices.
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 13 ©2013 Integrated Device Technology, Inc. Figure 5. ICS843004I-156 Application Schematic com mon mode center of the Receiv er. board at pins 21 and 20 respec tively.
25 MH z (1 8p f )
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 14 ©2013 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843004I-156. Equations and example calculations are also provided. The total power dissipation for the ICS843004I-156 is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 32.1°C/W per Table 6 below. Table 6. Thermal Resistance JA for 24 Lead TSSOP, E-Pad, Forced Convection
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 16 ©2013 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP, E-Pad
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 17 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP, E-Pad Table 8. Package Dimensions Reference Document: JEDEC Publication 95, MO-153 All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.10 A1 0.05 0.15 A2 0.85 0.95 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.50 0.70 P 5.0 5.5 P1 3.0 3.2 0° 8° aaa 0.076 bbb 0.10
ICS843004AGI-156 REVISION A FEBRUARY 27, 2013 18 ©2013 Integrated Device Technology, Inc. ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Ordering Information
Table 9. Ordering Information
ICS843004I-156 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved.
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