843004AGI-09LF

ICS843004I-09 RENESAS | Alldatasheet

Document overview

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Technical content

Features

• Four 3.3V differential LVPECL output pairs
• Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input
• Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
• VCO range: 560MHz – 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.54ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Frequency Select Function Table Inputs Output Frequency (MHz) (25MHz Reference)F_SEL1 F_SEL0 M Div. Value N Div. Value M/N Div. Value 0 0 25 4 6.25 156.25 01 2 5 5 5 1 2 5 1 0 25 10 2.5 62.5 1 1 25 Not Used Not Used Pin Assignment ICS843004I-09 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View nQ1 VCCO nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 nQ2 VCCO VEE nQ3 VCC nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT Phase Detector VCO 625MHz (w/25MHz Reference) OSC M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used nQ0 nQ1 F_SEL[1:0] nPLL_SEL nXTAL_SEL MR TEST_CLK XTAL_IN XTAL_OUT Pulldown Pulldown Pulldown Pulldown Pulldown nQ2 nQ3 Block Diagram

ICS843004AGI-09 REVISION A JUNE 28, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 3, 22 V CCO Power Output supply pins. 4, 5 Q0, nQ0 Output Differential output pair. LVPECL interface levels.

6 MR Input Pulldown

clock (PLL Bypass). LVCMOS/LVTTL interface levels. 9V CCA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 11, 18 V CC Power Core supply pins. XTAL_IN Input Parallel resonant crystal interface. XT AL_OUT is the output, XTAL_IN is the input. 15, 19 V EE Power Negative supply pins. 16 TEST_CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. inputs. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels.

ICS843004AGI-09 REVISION A JUNE 28, 2012 3 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 70C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 130 mA ICCA Analog Supply Current Included in I EE 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 120 mA ICCA Analog Supply Current Included in I EE 12 mA

ICS843004AGI-09 REVISION A JUNE 28, 2012 4 ©2012 Integrated Device Technology, Inc. NOTE 1: Outputs termination with 50 to VCCO – 2V. NOTE 1: Outputs termination with 50 to VCCO – 2V. Table 4. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

ICS843004AGI-09 REVISION A JUNE 28, 2012 5 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Table 5A. AC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE =0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Table 5B. AC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE =0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency Range F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.54 ps 125MHz, (1.875MHz – 20MHz) 0.58 ps 62.5MHz, (637kHz – 10MHz) 0.70 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency Range F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 50 ps tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.54 ps 125MHz, (1.875MHz – 20MHz) 0.58 ps 62.5MHz, (637kHz – 10MHz) 0.74 ps t R / tF Output Rise/Fall Time 20% to 80% 300 600 ps odc Output Duty Cycle 48 52 %

ICS843004AGI-09 REVISION A JUNE 28, 2012 6 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 156.25MHz (3.3V) 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.54ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS843004AGI-09 REVISION A JUNE 28, 2012 7 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 62.5MHz (3.3V) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 62.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.70ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

ICS843004AGI-09 REVISION A JUNE 28, 2012 8 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit Output Skew Output Duty Cycle/Pulse Width/Period 2.5V LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time SCOPE Qx nQx VEE VCC, -1.3V ± 0.165V VCCA, VCCO tsk(o) nQx Qx nQy Qy nQ0:nQ3 Q0:Q3 tPW tPERIOD tPW tPERIOD odc = x 100% SCOPE Qx nQx VEE VCC, -0.5V ± 0.125V VCCO VCCA, Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power 20% 80% 80% 20% tR tF VSWING nQ0:nQ3 Q0:Q3

ICS843004AGI-09 REVISION A JUNE 28, 2012 11 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS843004AGI-09 REVISION A JUNE 28, 2012 14 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843004I-09. Equations and example calculations are also provided. The total power dissipation for the ICS843004I-09 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection

ICS843004AGI-09 REVISION A JUNE 28, 2012 15 ©2012 Integrated Device Technology, Inc.

1. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

ICS843004AGI-09 REVISION A JUNE 28, 2012 16 ©2012 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 24 Lead TSSOP

ICS843004AGI-09 REVISION A JUNE 28, 2012 17 ©2012 Integrated Device Technology, Inc. ICS843004I-09 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS843004I-09 Data Sheet FEMTOCLOCK ® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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