ICS843004-125 IDT | Alldatasheet

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FemtoClock™ Crystal-to-3.3V LVPECL Frequency Synthesizer ICS843004-125 DATA SHEET ICS843004AG-125 REVISION A JUNE 3, 2009 1 ©2009 Integrated Device Technology, Inc. GENERAL DESCRIPTION The ICS843004-125 is a 4 output LVPECL Syn- thesizer optimized to generate Ethernet reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. The ICS843004-125 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843004-125 is packaged in a small 24-pin TSSOP package.

FEATURES

 Four 3.3V LVPECL output pairs  Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input  Crystal oscillator designed for 25MHz, 18pF parallel resonant crystal  Supports the following output frequency: 125MHz  VCO range: 560MHz - 680MHz  RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.58ps (typical)  Full 3.3V supply mode  0°C to 70°C ambient operating temperature  Available in lead-free (RoHS 6) package HiPerClockS™ ICS PIN ASSIGNMENT ICS843004-125 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View nQ1 VCCo nQ0 MR nPLL_SEL nc VCCA nc VCC nc nQ2 VCCO nQ3 VEE VCC nXTAL_SEL REF_CLK VEE XTAL_IN XTAL_OUT BLOCK DIAGRAM stupnI )zHM(ycneuqerFtuptuO ).feRzHM52(eulaVrediviDMe ulaVrediviDNe ulaVrediviDN/M 525 5 5 21 FREQUENCY SELECT FUNCTION TABLE 1 1 Phase Detector VCO 625MHz (w/25MHz Reference) OSC M = 25 (fixed) nQ0 nQ1 nQ1 nQ2 nQ3 nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR Pulldown Pulldown Pulldown Pulldown 25MHz ÷5

ICS843004AG-125 REVISION A JUNE 3, 2009 2 ©2009 Integrated Device Technology, Inc. TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

ICS843004AG-125 REVISION A JUNE 3, 2009 3 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V EE = 0V, TA = 0°C TO 70°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V EE = 0V, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 2V CC 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tupnI tnerruChgiH ,RM,KLC_FER LES_LATXn,LES_LLPn V CC V= NI V564.3=0 51A µ I LI tupnI tnerruCwoL ,RM,KLC_FER LES_LATXn,LES_LLPn V CC V,V564.3= NI V0=5 -A µ ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 82.3°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanA V CC 51.0–3 .3V CC V V OCC egatloVylppuStuptuO 531.33 .35 64.3V I EE tnerruCylppuSrewoP 031A m I ACC tnerruCylppuSgolanAI nidedulcnI EE 51A m TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V EE = 0V , TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HO 1ETON;egatloVhgiHtuptuO V OCC 4.1-V OCC 9.0-V V LO 1ETON;egatloVwoLtuptuO V OCC 0.2-V OCC 7.1-V V GNIWS gniwSegatloVtuptuOkaeP-ot-kaeP 6.00 .1V 05htiwdetanimretstuptuO:1ETON Ω Vot OCC .V2-

ICS843004AG-125 REVISION A JUNE 3, 2009 4 ©2009 Integrated Device Technology, Inc. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, V TABLE 4. CRYSTAL CHARACTERISTICS

ICS843004AG-125 REVISION A JUNE 3, 2009 5 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.58ps (typical) OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ NOISE POWER dBc Hz 10Gb Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding 10Gb Ethernet Filter to raw data

ICS843004AG-125 REVISION A JUNE 3, 2009 6 ©2009 Integrated Device Technology, Inc. ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION tPW tPERIOD tPW tPERIOD odc = x 100% Q0:Q3 RMS PHASE JITTER OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx nQx LVPECL VEE -1.3V±0.165V OUTPUT RISE/FALL TIME VCC, VCCO nQ0:nQ3 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD t sk(o) Qy Qx nQy nQx Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power VCCA 20% 80% 80% 20% tR tF VSWING Q0:Q3 nQ0:nQ3

ICS843004AG-125 REVISION A JUNE 3, 2009 10 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS843004-125. Equations and example calculations are also provided. The total power dissipation for the ICS843004-125 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 130mA = 450.45mW
  • Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power _MAX (3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (multi-layer).

TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 24-PIN TSSOP, FORCED CONVECTION

ICS843004AG-125 REVISION A JUNE 3, 2009 11 ©2009 Integrated Device Technology, Inc.

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

ICS843004AG-125 REVISION A JUNE 3, 2009 12 ©2009 Integrated Device Technology, Inc. TABLE 7. θ

ICS843004AG-125 REVISION A JUNE 3, 2009 13 ©2009 Integrated Device Technology, Inc. TABLE 9. ORDERING INFORMATION

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San Jose, CA 95138 ICS43004-125 Data Sheet FEMTOCLOCK™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved. www.IDT.com