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Femtoclocks® Crystal-to-3.3V LVPECL Frequency Synthesizer 843004-01 Data Sheet ©2016 Integrated Device Technology, Inc Revision B January 18, 20161 GENERAL DESCRIPTION The 843004-01 is a 4 output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of the family of high performance clock solutions from IDT. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, 62.5MHz. The 843004-01 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843004-01 is packaged in a small 24-pin TSSOP package.
FEATURES
Four 3.3V LVPECL outputs Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.57ps (typical) RMS phase noise at 156.25MHz (typical) Phase noise: Offset Noise Power Full 3.3V supply mode -30°C to 85°C ambient operating temperature Available in lead-free RoHS compliant package PIN ASSIGNMENT Phase Detector VCO 625MHz (w/25MHz Reference) OSC M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used 843004-01 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View nQ1 VCCo nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC F_SEL1 nQ2 V CCO nQ3 VEE VCC nXTAL_SEL TEST_CLK VEE XTAL_IN XTAL_OUT BLOCK DIAGRAM Inputs Output Frequency (25MHz Ref.)F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Divider Value 0 0 25 4 6.25 156.25 0 1 25 5 5 125 1 0 25 10 2.5 62.5 1 1 25 not used not used FREQUENCY SELECT FUNCTION TABLE F_SEL[1:0] nPLL_SEL TEST_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR nQO nQ1 nQ2 nQ3 Pulldown Pulldown 25MHz Pulldown Pulldown Pulldown
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 16 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input. source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels. Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc Revision B January 18, 20163 TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCA = V CCO TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCA = V CCO Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage nPLL_SEL, nXTAL_SEL, F_SEL0, F_SEL1, MR -0.3 0.8 V TEST_CLK -0.3 1.3 V I IH Input High Current TEST_CLK, MR, nPLL_ SEL, nXTAL_SEL, F_SEL0, F_SEL1 V CC = V IN = 3.465V 150 µA I IL Input Low Current TEST_CLK, MR, nPLL_ SEL, nXTAL_SEL, F_SEL0, F_SEL1 V CC = 3.465V, V IN = 0V -5 µA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 70°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage 3.135 3.3 3.465 V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 135 mA I CCA Analog Supply Current Included in I EE 15 mA TABLE 3C. LVPECL DC CHARACTERISTICS, V CC = V CCA = V CCO Symbol Parameter Test Conditions Minimum Typical Maximum Units V OH Output High Voltage; NOTE 1 V CCO - 1.4 V CCO - 0.9 V V OL Output Low Voltage; NOTE 1 V CCO - 2.0 V CCO - 1.7 V V SWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to V CCO - 2V.
TABLE 5. AC CHARACTERISTICS, V TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used.
©2016 Integrated Device Technology, Inc Revision B January 18, 20165 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.63ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 125MHZ TYPICAL PHASE NOISE AT 62.5MHZ0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.81ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Raw Phase Noise Data 100 1k 10k 100k 1M 10M 100M Phase Noise Result by adding 10Gb Ethernet Filter to raw data 10Gb Ethernet Filter Phase Noise Result by adding 10Gb Ethernet Filter to raw data 10Gb Ethernet Filter Raw Phase Noise Data
©2016 Integrated Device Technology, Inc Revision B January 18, 20166 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 156.25MHZ -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.57ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz Phase Noise Result by adding 10Gb Ethernet Filter to raw data Raw Phase Noise Data 10Gb Ethernet Filter
©2016 Integrated Device Technology, Inc Revision B January 18, 20167 PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
This section provides information on power dissipation and junction temperature for the 843004-01. Equations and example calculations are also provided. The total power dissipation for the 843004-01 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 135mA = 467.8mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power _MAX (3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.588W * 65°C/W = 123.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 7. θ
TABLE 8. PACKAGE DIMENSIONS
TABLE 9. ORDERING INFORMATION
©2016 Integrated Device Technology, Inc Revision B January 18, 201616 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T5 4 AC Characteristics Table - deleted Propagation Delay row. 5/6/05 B Features Section - added lead-free bullet. Added - LVCMOS to XTAL Interface and Recommendations for Unused Input and Output Pins sections. Ordering Information Table - added lead-free part number, marking and note. 6/30/06 Updated datasheet format. 12/9/14 B T9 General Description - Removed Hiperclocks and changed ICS to IDT. Ordering Information - Removed ICS in the Part/Order number and removed LF note below the table. Updated data sheet header and footer. 1/18/16
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters
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