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Crystal-to-3.3V LVPECL Frequency Synthesizer 843004-125 Data Sheet ©2016 Integrated Device Technology, Inc January 18, 20161 GENERAL DESCRIPTION The 843004-125 is a 4 output LVPECL Syn- thesizer optimized to generate Ethernet reference clock frequencies and is a member of the family of high performance clock solutions from IDT. The 843004-125 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843004-125 is packaged in a small 24-pin TSSOP package.
FEATURES
Four 3.3V LVPECL output pairs Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Crystal oscillator designed for 25MHz, 18pF parallel resonant crystal Supports the following output frequency: 125MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.58ps (typical) Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package PIN ASSIGNMENT 843004-125 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View nQ1 VCCo nQ0 MR nPLL_SEL nc VCCA nc VCC nc nQ2 V CCO nQ3 VEE VCC nXTAL_SEL REF_CLK VEE XTAL_IN XTAL_OUT BLOCK DIAGRAM Inputs Output Frequency (MHz) (25MHz Ref.)M Divider Value N Divider Value M/N Divider Value 25 5 5 125 FREQUENCY SELECT FUNCTION TABLE Phase Detector VCO 625MHz (w/25MHz Reference) OSC M = 25 (fixed) nQ0 nQ1 nQ1 nQ2 nQ3 nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR Pulldown Pulldown Pulldown Pulldown 25MHz ÷5
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 8, 10, 12 nc Unused No connect. XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. 16 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels. Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc January 18, 20163 TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, V EE = 0V, TA = 0°C TO 70°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, V EE = 0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V CC + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL V CC = V IN = 3.465V 150 µA I IL Input Low Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL V CC = 3.465V, VIN = 0V -5 µA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 82.3°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V CC Core Supply Voltage 3.135 3.3 3.465 V V CCA Analog Supply Voltage V CC – 0.15 3.3 V CC V V CCO Output Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 130 mA I CCA Analog Supply Current Included in I EE 15 mA TABLE 3C. LVPECL DC CHARACTERISTICS, V CC = V CCO = 3.3V±5%, V EE = 0V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V OH Output High Voltage; NOTE 1 V CCO - 1.4 V CCO - 0.9 V V OL Output Low Voltage; NOTE 1 V CCO - 2.0 V CCO - 1.7 V V SWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to V CCO - 2V.
TABLE 5. AC CHARACTERISTICS, V TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF , parallel resonant crystal. thermal equilibrium has been reached under these conditons. NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used.
©2016 Integrated Device Technology, Inc January 18, 20165 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.58ps (typical) OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ NOISE POWER dBc Hz 10Gb Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding 10Gb Ethernet Filter to raw data
©2016 Integrated Device Technology, Inc January 18, 20166 PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
This section provides information on power dissipation and junction temperature for the 843004-125. Equations and example calculations are also provided. The total power dissipation for the 843004-125 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 130mA = 450.45mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power _MAX (3.465V, with all outputs switching) = 450.45mW + 120mW = 570.45mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 7. θ
TABLE 9. ORDERING INFORMATION
©2016 Integrated Device Technology, Inc January 18, 201614 REVISION HISTORY SHEET Rev Table Page Description of Change Date AT 9 Removed ICS from the part number where needed. General Description - Removed ICS Chip and Hiperclocks. Ordering Information - Removed quantity from tape and reel. Deleted LF note below the table. Updated Header and footer. 1/18/16
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