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Document overview
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- PDF pages: 21
Technical content
Features
- Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs
- Using a 31.25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
- VCO range: 560MHz – 700MHz
- RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.51ps (typical) Offset Noise Power
- Full 3.3V supply mode
- 0°C to 70°C ambient operating temperature
- Industrial temperature available upon request
- Available in ead-free (RoHS 6) package Pin Assignment 843003 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package DIV_SELB0 VCO_SEL MR VCCO_A QA0 nQA0 OEB OEA FB_DIV VCCA VCC DIV_SELA0 DIV_SELB1 VCCO_B nQB0 QB0 nQB1 QB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT VEE DIV_SELA1 Block Diagram Phase Detector VCO 625MHz 0 = ÷20 (default) 1 = ÷24 0 0 ÷1 0 1 ÷2 (default) 1 0 ÷4 1 1 ÷5 0 0 ÷1 0 1 ÷2 1 0 ÷4 (default) 1 1 ÷5 FB_DIV OSC QA0 nQA0 QB0 nQB0 QB1 nQB1 Pullup Pulldown Pulldown:Pullup Pullup Pulldown Pulldown Pullup Pullup:Pulldown Pullup OEA DIV_SELA[1:0] VCO_SEL TEST_CLK MR OEB DIV_SELB[1:0] FB_DIV XTAL_OUT XTAL_SEL XTAL_IN
843003 DATA SHEET
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1 DIV_SELB0 Input Pulldown Division select pin for Bank B. Default = Low. LVCMOS/LVTTL interface levels.
2 VCO_SEL Input Pullup
dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels.
3 MR Input Pulldown
causing the true outputs Qx to go low and the inverted outputs nQx to go high. pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. 4V CCO_A Power Output supply pin for Bank A outputs. 5, 6 QA0, nQA0 Output Diffe rential output pair. LVPECL interface levels.
7 OEB Input Pullup
state of outputs are enabled. LVCMOS/LVTTL interface levels.
8 OEA Input Pullup
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. 9 FB_DIV Input Pulldown Feedback divide select. When Low (default), the feedback divider is set for ÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels. CCA Power Analog supply pin. 11 V CC Power Core supply pin. 12 DIV_SELA0 Input Pullup Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels. 13 DIV_SELA1 Input Pulldown Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels. 14 V EE Power Negative supply pin.
16 XTAL_OUT,
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. single-ended reference clock.
17 TEST_CLK Input Pulldown
state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels.
18 XTAL_SEL Input Pullup
default. LVCMOS/LVTTL interface levels. 19, 20 nQB1, QB1 Output Differential ou tput pair. LVPECL interface levels. 21, 22 nQB01, QB0 Output Dif ferential output pair. LVPECL interface levels. 23 V CCO_B Power Output supply pin for Bank B outputs. 24 DIV_SELB1 Input Pullup Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels.
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Table 2. Pin Characteristics
Figure 1. OE Timing Diagram
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 70C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO_A, VCCO_B Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 158 mA ICCA Analog Supply Current 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage DIV_SEL[A0:A1], FB_DIV, DIV_SEL[B0:B1], OEA, OEB, VCO_SEL, XTAL_SEL, MR -0.3 0.8 V TEST_CLK -0.3 1.3 V IIH Input High Current TEST_CLK, FB_DIV, MR, DIV_SELA1, DIV_SELB0 VCC = VIN = 3.465V 150 µA OEA, OEB, VCO_SEL, XTAL_SEL, DIV_SELB1, DIV_SELA0 VCC = VIN = 3.465V 5 µA IIL Input Low Current TEST_CLK, FB_DIV, MR, DIV_SELA1, DIV_SELB0 VCC = 3.465V, VIN = 0V -5 µA OEA, OEB, VCO_SEL, XTAL_SEL, DIV_SELB1, DIV_SELA0 VCC = 3.465V, VIN = 0V -150 µA
NOTE 1: Outputs termination with 50 to VCCO_A, _B – 2V. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. Table 6. AC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 125MHz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)
Rev A 4/7/15 8 FEMTOCLOCKS™ CRYST AL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 156.25MHz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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Typical Phase Noise at 312.5MHz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 312.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.50ps Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)
Rev A 4/7/15 10 FEMTOCLOCKS™ CR YSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 625MHz 10Gb Ethernet Filter Phase Noise Result by adding a 10Gb Ethernet filter to raw data Raw Phase Noise Data 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.42ps Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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Parameter Measurement Information LVPECL Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period Output Skew Bank Skew Output Rise/Fall Time SCOPE Qx nQx VEE VCC, 2V% 1.3V ± 0.165V- VCCA, VCCO_A, _B Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQA0, nQB0, nQB1 QA0, QB0, QB1 nQx Qx nQy Qy nQB0 QB0 nQB1 QB1 tsk(b) Clock Outputs 20% 80% 80% 20% tR tF VSWING
Rev A 4/7/15 12 FEMTOCLOCKS™ CR YSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843003 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, VCCA and VCCO_x should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin. Figure 2. Power Supply Filtering resistor can be tied from the TEST_CLK to ground. protection. A 1k resistor can be used. pair should either be left floating or terminated.
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Figure 3. Crystal Input Interface Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
Rev A 4/7/15 14 FEMTOCLOCKS™ CR YSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V
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C2 may be slightly adjusted for optimizing frequency accuracy. Table 7. There should be at least one decoupling capacitor per has clean analog power ground plane.
24 DIV_SELB0
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This section provides information on power dissipation and junction temperature for the 843003. Equations and example calculations are also provided. The total power dissipation for the 843003 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8below. of board (single layer or multi-layer). Table 8. Thermal Resitance JA for 24 Lead TSSOP, Forced Convection
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- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 9. JA vs. Air Flow Table for a 24 Lead TSSOP
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
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Ordering Information
Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev A 4/7/15 20 FEMTOCLOCKS™ CR YSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Rev Table Page Description of Change Date A T10 Features Section - added Lead-Free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information table - added Lead-Free part number, marking and note. 1/25/06 A T3B 3 Bank B Frequency Table - corrected table labeling. Added LVCMOS to XTAL Interface section. Updated datasheet format. 2/19/08 Updated data sheet format. 4/7/15
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