843002I-40 IDT | Alldatasheet
Document overview
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Technical content
Features
- Two Differential LVPECL outputs
- Selectable CLKx, nCLKx differential input pairs
- CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels
- Maximum output frequency: 175MHz
- FemtoClock VCO frequency range: 560MHz - 700MHz
- RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical)
- Full 3.3V or mixed 3.3V core/2.5V output operating supply
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Pin Assignment ICS843002I-40 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 LF1 LF0 ISET VCC CLK0 nCLK0 CLK_SEL nc LOR0 LOR1 nc VCCO_LVCMOS VCCO_LVPECL nQB QB VEE QA_SEL1 QA_SEL0 nc QB_SEL1 QB_SEL0 VCCA QA nQA XTAL_OUT R_SEL2 R_SEL1 R_SEL0 VEE CLK1 nCLK1 XTAL_IN
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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R Divider = 1, 2, 4, 8, 16 or 32CLK1 nCLK1 Activity Detector CLK0 nCLK0 Activity Detector LOR1 LOR0 R_SEL2:0 3 ISET CLK_SEL FemtoClock PLL x32
622.08 MHz
VCCO_LVPECL QA nQAC0 Divider = 4, 8, 32, or HiZ QB nQBC1 Divider = QB_SEL1:0 QA_SEL1:0 VCXO Charge Pump and Loop Filter External Loop Components
19.44 MHz
XTAL_INXTAL_OUTLF1LF0 Divide by 32 Divide by 32 VCXO Jitter Attenuation PLL Phase Detector ICS843002I-40 110 110 111 111 VCCO_LVCMOS 4, 8, 32, or HiZ NOTE: 19.44MHz VCXO crystal shown is typical for SONET/SDH device applications.
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Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Input/Output Loop filter connection node pins.
3 ISET Analog
Input/Output Charge pump current setting pin. 4V CC Power Core power supply pin. 5 CLK0 Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 7 CLK_SEL Input Pulldown Input clock select. LVCMOS/LVTTL interface levels. See Table 3A. 8, 11, 22 nc Unused No connect. QA_SEL0 Input Pullup Output divider control for QA/nQA LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. QB_SEL0 Input Pullup Output divider control for QB/nQB LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. 14 V CCA Power Analog supply pin. 15, 16 QA, nQA Output Differential clock ou tput pair. LVPECL interface levels. 17, 27 V EE Power Negative supply pins. 18, 19 QB, nQB Output Differential clock ou tput pair. LVPECL interface levels. 20 V CCO_LVPECL Power Output supply pi n for LVPECL outputs. 21 V CCO_LVCMOS Power Output supply pin for LVCMOS/LVTTL outputs. 23 LOR1 Output Alarm output, loss of reference for CLK1/nCLK1. LVCMOS/LVTTL interface levels. 24 LOR0 Output Alarm output, loss of reference for CLK0/nCLK0. LVCMOS/LVTTL interface levels. Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 26 CLK1 Input Pulldown Non-inverting differential clock input. Input Pulldown Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B. XTAL_IN Input Crystal oscillator interface. The XTAL_IN is the input.
Rev C 9/4/14 4 175MHZ, FEMTOCLOCK ® VCXO BASED SONET/SDH JITTER ATTENUATORS 843002I-40 DATA SHEET Function Tables Table 3A. Input Reference Selection Function Table Table 3B. Input Reference Divider Selection Function Table Table 3C. Output Divider Selection Function Table Input Function CLK_SEL Input Selected
0 CLK0/nCLK0
1 CLK1/nCLK1
R_SEL2 R_SEL1 R_SEL0 R Di vider Value or State 000 ÷ 1 001 ÷ 2 010 ÷ 4 011 ÷ 8 100 ÷ 16 101 ÷ 32 1 1 0 bypass VCXO PLL 1 1 1 bypass VCXO and FemtoClock PLLs Inputs Function QX_SEL1 QX_SEL0 Output Divider Value or State 0 0 Output QX/nQX (High-Impedance) 01 ÷ 32 10 ÷ 8 11 ÷ 4
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuos Current Surge Current -0.5V to VCCO_LVCMOS + 0.5V 50mA 100mA Package Thermal Impedance, JA 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.15 3.3 V CC V VCCO_LVCMOS, VCCO_LVPECL Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IEE Power Supply Current 210 mA ICCA Analog Supply Current 15 mA
Rev C 9/4/14 6 175MHZ, FEMTOCLOCK ® VCXO BASED SONET/SDH JITTER ATTENUATORS 843002I-40 DATA SHEET Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VCC = 3.3V±5%, VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: VIL cannot be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VCCO_LVPECL – 2V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current QA_SEL[0:1], QB_SEL[0:1] VCC = VIN = 3.465V 5 µA CLK_SEL, R_SEL[0:2] VCC = VIN = 3.465V 150 µA IIL Input Low Current QA_SEL[0:1], QB_SEL[0:1] VCC = 3.465V, VIN = 0V -150 µA CLK_SEL, R_SEL[0:2] VCC = 3.465V, VIN = 0V -5 µA VOH Output High Voltage LOR0, LOR1 VCCO_LVCMOS = 3.465V, IOH = 1mA 2.6 V VCCO_LVCMOS = 2.625V, IOH = 1mA 1.8 V VOL Output Low Voltage LOR0, LOR1 VCCO_LVCMOS = 3.465V or 2.625V, IOL= -1mA 0.5 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK0/nCLK0, CLK1/nCLK1 VCC = VIN = 3.465V 150 µA IIL Input Low Current CLK0, CLK1 V CC = 3.465V, VIN = 0V -5 µA nCLK0, nCLK1 V CC = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 V EE + 0.5 V CC – 0.85 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCCO – 1.4 V CCO – 0.9 V VOL Output Low Voltage; NOTE 1 VCCO – 2.0 V CCO – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V
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NOTE 1: Outputs terminated with 50 to VCCO_LVPECL – 2V. Table 5. AC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V, See Parameter Measurement Information section. has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise plots.
Rev C 9/4/14 8 175MHZ, FEMTOCLOCK ® VCXO BASED SONET/SDH JITTER ATTENUATORS 843002I-40 DATA SHEET Typical Phase Noise at 155.52MHz Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical) Offset Frequency (Hz) Noise Power dBc Hz
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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Parameter Measurement Information 3.3V Core/3.3V LVPECL Output Load AC Test Circuit Differential Input Level RMS Phase Jitter 3.3V Core/2.5V LVPECL Output Load AC Test Circuit Output Skew Output Rise/Fall Time -1.3V ± 0.165V VCC, VCCA VCCO_L VPECL, VCCO_L VCMOS nCLK0, nCLK1 CLK0, CLK1 VCMR Cross Points VPP VCC VEE Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPEQx nQx VEE -0.5V ± 0.125V 2.8V ± 0.04V 2.8V ± 0.04V VCC, VCCA VCCO_L VPECL VCCO_L VCMOS nQx Qx nQy Qy nQA, nQB QA, QB
Rev C 9/4/14 10 175MHZ, FEMTOCLO CK® VCXO BASED SONET/SDH JITTER ATTENUATORS 843002I-40 DATA SHEET Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLKx to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. nQA, nQB QA, QB
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bypass capacitors should be used for each pin. Figure 1. Power Supply Filtering Figure 2. Single-Ended Signal Driving Differential Input
Rev C 9/4/14 14 175MHZ, FEMTOCLO CK® VCXO BASED SONET/SDH JITTER ATTENUATORS 843002I-40 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50LVPECL Input 3.3V 3.3V
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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Termination for 2.5V LVPECL Outputs Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. Figure 6A. 2.5V LVPECL Driver Termination Example Figure 6C. 2.5V LVPECL Driver Termination Example Figure 6B. 2.5V LVPECL Driver Termination Example 2.5V LVPECL Driver VCC = 2.5V 2.5V 2.5V 50Ω 50Ω 250 Ω 250 Ω 62.5 Ω 62.5 Ω 2.5V LVPECL Driver VCC = 2.5V 2.5V 50Ω 50Ω Ω Ω 2.5V LVPECL Driver VCC = 2.5V 2.5V 50Ω 50Ω Ω Ω Ω
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal’s load capacitance CL characteristic determines it resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal (CL) is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and CP values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. VCXO Characteristics Table VCXO-PLL Loop Bandwidth Selection Table Crystal Characteristics LF0 LF1 ISET XTAL_IN XTAL_OUT R S CSCP RSET CTUNE CTUNE 19.44MHz Symbol Parameter Typical Units kVCXO VCXO Gain 5800 Hz/V CV_LOW Low Varactor Capacitance 12.6 pF CV_HIGH High Varactor Capacitance 24.5 pF Bandwidth Crystal Frequency (MHz) R S (k)C S (µF) C P (µF) R SET (k) 10Hz (Low) 19.44 5 1.0 0.10 9.5 70Hz (Mid) 19.44 10 1.0 0.01 4.75 100Hz (High) 19.44 15 1.0 0.01 4.75 Symbol Parameter Test Conditions Minimum Typical Maximum Units Mode of Oscillation Fundamental fN Frequency 19.44 MHz fT Frequency Tolerance ±20 ppm fS Frequency Stability ±20 ppm Operating Temperature Range -40 +85 0C CL Load Capacitance 12 pF CO Shunt Capacitance 4 pF CO / C1 Pullability Ratio 220 240 ESR Equivalent Series Resistance 50 Drive Level 1m W Aging @ 25 0C ±3 per year ppm
This section provides information on power dissipation and junction temperature for the ICS843002I-40. Equations and example calculations are also provided. The total power dissipation for the ICS843002I-40 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance JA for 48 Lead TQFP, Forced Convection
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- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. Figure 8. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
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dimensions are in Table 8 below. Table 8. Package Dimensions
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
175MHZ, FEMTOCLOCK® VCXO BASED SONET/SDH JITTER ATTENUATORS
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Rev Table Page Description of Change Date A T4B 6 LVCMOS DC Characteristics Table - added conditions to V OH and VOL. 1/22/09 B T5 7 AC Characteristics Table - changed output skew from 50ps max. to 150ps max. 4/27/09 C T9 22 Remove leaded parts from orderables table 11/13/12 C 1 General Description - Removed Loopbanwidth Updated datasheet format 9/4/14
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