843002I-01

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FemtoClocks® Crystal-to- 3.3V, 2.5V LVPECL Frequency Synthesizer 843002I-01 DATASHEET 843002I-01 REVISION A 2/20/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843002I-01 is a 2 output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The 843002I-01 uses IDT’s FemtoClock ® low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernetjitter requirements. The 843002I-01 is packaged in a small 20-pin TSSOP package.

FEATURES

 Two 3.3V or 2.5V LVPECL outputs  Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input  Supports the following output frequencies: 156.25MHz, 125MHz and 62.5MHz  VCO range: 560MHz - 680MHz  RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.55ps (typical)  Output skew: 30ps (maximum)  Supply Voltage Modes Core/Outputs 3.3/3.3 2.5/2.5  -40°C to 85°C ambient operating temperature  Available in lead-free RoHS-compliant package PIN ASSIGNMENT Phase Detector VCO 625MHz (w/25MHz Reference) M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 (default) 0 1 ÷5 1 0 ÷10 1 1 ÷5 OSC 843002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View BLOCK DIAGRAM FREQUENCY SELECT FUNCTION TABLE F_SEL[1:0] nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR nQ0 nQ1 Pulldown Pulldown 25MHz nc VCCO nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC V CCO nQ1 V EE VCC nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 Pulldown Pulldown Pulldown Inputs Output Frequency (25MHz Ref.)F_SEL1 F_SEL0 M Divider Value N Divider Value 0 0 25 4 156.25 (default) 0 1 25 5 125 1 0 25 10 62.5 1 1 25 5 125

2 REVISION A 2/20/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 2, 20 V CCO Power Output supply pins. 3, 4 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.

5 MR Input Pulldown

abled. LVCMOS/LVTTL interface levels. CCA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10, 16 V CC Power Core supply pin. 14 REF_CLK Input Pulldown LVCMOS/LVTTL reference clock input. source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. EE Power Negative supply pins. 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 FEMTOCLOCKS® CRYSTAL-TO-

3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -40°C TO 85°C TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3.3 3.63 V VCCO Output Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 130 mA ICCA Analog Supply Current 13 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.375 2.5 2.625 V VCCA Analog Supply Voltage 2.375 2.5 2.625 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 115 mA ICCA Analog Supply Current 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.3V 2 V CC + 0.3 V VCC = 2.5V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V IIH Input High Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = VIN = 3.63V or 2.625V 150 µA IIL Input Low Current REF_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = VIN = 3.63V or 2.625V -5 µA

4 REVISION A 2/20/15

TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Measured using crystal input. For Notes, see Table 5A above.

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3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Phase Noise Result by adding

10 Gigabit Ethernet Filter to raw data

10 Gigabit Ethernet Filter

156.25MHz RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.55ps (typical)

FEMTOCLOCKS® CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET

6 REVISION A 2/20/15

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT PARAMETER MEASUREMENT INFORMATION OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIODOUTPUT SKEW

7 FEMTOCLOCKS® CRYSTAL-TO-

3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843002I-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01 μF bypass capacitor should be connected to each V CCA. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING FIGURE 2. CRYSTAL INPUT INTERFACE

FEMTOCLOCKS® CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET

8 REVISION A 2/20/15

TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. INPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. REF_CLK I NPUT: For applications not requiring the use of the reference clock, it can be left fl oating. Though not required, but for additional protection, a 1k Ω resistor can be tied from the REF_CLK to ground. LVCMOS C ONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

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3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to V CC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE Zo = 50 Ohm VCCO=2.5V Zo = 50 Ohm 2.5V 2,5V LVPECL Driver FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE VCCO=2.5V Zo = 50 Ohm 2,5V LVPECL Driver Zo = 50 Ohm 2.5V FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 62.5 2.5V 2,5V LVPECL Driver 250 Zo = 50 Ohm Zo = 50 Ohm 62.5 2.5V 250 VCCO=2.5V

10 REVISION A 2/20/15

example of LVEPCL termination is shown in this schematic. for optimizing frequency accuracy. Figure 5B shows an example of 843002I-01 P .C. board layout. of either surface mount HC49S or through-hole HC49 package. the board has clean analog power ground plane. shown in this layout example. TABLE 6. FOOTPRINT TABLE

25 MHz

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This section provides information on power dissipation and junction temperature for the 843002I-01. Equations and example calculations are also provided. The total power dissipation for the 843002I-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 130mA = 471.9mW
• Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION

12 REVISION A 2/20/15

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

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TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

14 REVISION A 2/20/15

TABLE 9. PACKAGE DIMENSIONS

15 FEMTOCLOCKS® CRYSTAL-TO-

TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

FEMTOCLOCKS® CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 843002I-01 DATA SHEET

16 REVISION A 2/20/15

Rev Table Page Description of Change Date A T10 15 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 12/14/10 Updated data sheet format 2/20/15

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.