ICS843002I-72 IDT | Alldatasheet
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FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR ICS843002I-72 IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 1 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 GENERAL DESCRIPTION The ICS843002I-72 is a member of the HiperClock S ™ family of high performance clock solutions from IDT. The ICS843002I-72 is a PLL based synchronous clock generator that is optimized for WCDMA channel card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the second PLL stage. The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock™ VCO. The device performance and the PLL multiplication ratios are optimized to support WCDMA applications. The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The ICS843002I-72 can accept a single-ended input. LOCK_DT reports the lock status of VCXO PLL loop. If the reference clock input is lost, it will set LOCK_DT to logic LOW. Typical ICS843002I-72 configuration in WCDMA Systems: 19.2MHz pullable crystal Input Reference clock frequency: 3.84MHz Output clock frequency: 122.88MHz PIN ASSIGNMENT
FEATURES
- Two differential LVPECL outputs
- CLK input accepts the following input levels: LVCMOS or LVTTL levels
- Output frequency: 122.88MHz (typical)
- FemtoClock VCO frequency range: 490MHz - 680MHz
- RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal (1.875MHz to 10MHz): 0.49ps (typical)
- Deterministic jitter: 30fs (typical)
- Random jitter, RMS: 2.2ps (typical)
- Full 3.3V or mixed 3.3V core/2.5V output supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package HiPerClockS™ ICS ICS843002I-72 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 LOCK_DT V EE VCC VCCO VCCO nQ1 VEE VEE VEE nOE VCCA VEE VCCO nQ0 nc VEE VEE VCC VCC VCC XTAL_OUT XTAL_IN LF1 LF0 ISET VCC VCC VEE VEE CLK
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 2 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR BLOCK DIAGRAM NOTE 1: 19.2MHz pullable crystal shown is typical for WCDMA device applications. CLK FemtoClock x32 VCXO Charge Pump LF nQ0 LF0 LF1 19.2MHz Pullable Xtal LOCK_DT XTAL_IN XTAL_OUT 122.88MHz nQ1 nOE 3.84MHz Pulldown ISET ÷5 Phase Detect External Loop Components Pulldown
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. INPUT REFERENCE SELECTION FUNCTION TABLE
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 4 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI tupnIe gatloVhgiH2 V CC 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tnerruChgiHtupnIE On,KLCV CC V= NI V564.3=0 51A µ I LI tupnIt nerruCwoLE On,KLCV CC V,V564.3= NI V0=5 -A µ TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HO 1ETON;egatloVhgiHtuptuOV OCC 4.1-V OCC 9.0-V V LO 1ETON;egatloVwoLtuptuOV OCC 0.2-V OCC 7.1-V V GNIWS gniwSegatloVtuptuOkaeP-ot-kaeP 6.00 .1V 05htiwdetanimretstuptuO:1ETON Ω Vot OCC ,noitces"noitamrofnItnemerusaeMretemaraP"eeS.V2- .smargaid"tiucriCtseTdaoLtuptuO" lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanAV CC 31.0–3 .3V CC V V OCC egatloVylppuStuptuO 531.33 .35 64.3V I EE tnerruCylppuSrewoP 041A m I ACC tnerruCylppuSgolanA 31A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V CC egatloVylppuSeroC 531.33 .35 64.3V V ACC egatloVylppuSgolanAV CC 31.0–3 .3V CC V V OCC egatloVylppuStuptuO 573.25 .25 26.2V I EE tnerruCylppuSrewoP 041A m I ACC tnerruCylppuSgolanA 31A m
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 5 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR TABLE 5A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C TABLE 5B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU F TUO ycneuqerFtuptuO 88.221z HM t )ø(tij ;)modnaR(,rettiJesahPSMR 1ETON :egnarnoitargetnI,zHM88.221 zHM01-zHM578.1 94.0s p t JD 2ETON;rettiJcitsinimreteD 03s f t JR 2ETON;SMR,rettiJmodnaR 2.2s p t )o(ks4 ,3ETON;wekStuptuO 05s p tR t/ F emiTllaF/esiRtuptuO% 08ot%020 030 55s p cdoe lcyCytuDtuptuO 941 5% .noitcesnoitamrofnItnemerusaeMretemaraPeeS .tolPesioNesahPehtotreferesaelP:1ETON .0003-AIStsercevaWgnisuderusaeM:2ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON .stniopssorclaitnereffidtuptuoehttaderusaeM .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU F TUO ycneuqerFtuptuO 88.221z HM t )ø(tij ;)modnaR(,rettiJesahPSMR 1ETON :egnarnoitargetnI,zHM88.221 zHM01-zHM578.1 94.0s p t JD 2ETON;rettiJcitsinimreteD 03s f t JR 2ETON;SMR,rettiJmodnaR 2.2s p t )o(ks4 ,3ETON;wekStuptuO 05s p tR t/ F emiTllaF/esiRtuptuO% 08ot%020 030 55s p cdoe lcyCytuDtuptuO 941 5% .noitcesnoitamrofnItnemerusaeMretemaraPeeS .tolPesioNesahPehtotreferesaelP:1ETON .0003-AIStsercevaWgnisuderusaeM:2ETON .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON .stniopssorclaitnereffidtuptuoehttaderusaeM .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HO 1ETON;egatloVhgiHtuptuOV OCC 4.1-V OCC 9.0-V V LO 1ETON;egatloVwoLtuptuOV OCC 0.2-V OCC 5.1-V V GNIWS gniwSegatloVtuptuOkaeP-ot-kaeP 4.00 .1V 05htiwdetanimretstuptuO:1ETON Ω Vot OCC ,noitces"noitamrofnItnemerusaeMretemaraP"eeS.V2- .smargaid"tiucriCtseTdaoLtuptuO"
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 6 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR TYPICAL PHASE NOISE AT 122.88MHZ @ 3.3V/3.3V 122.88MHz RMS Phase Jitter (Random) 1.875MHz to 10MHz = 0.49ps (typical) OFFSET FREQUENCY (HZ) 10Gb Ethernet Filter Raw Phase Noise Data Phase Noise Result by adding 10Gb Ethernet Filter to raw data NOISE POWER dBc Hz
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 7 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION OUTPUT RISE/FALL TIME 3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT SCOPEQx nQx LVPECL VEE 2.8V±0.04V -0.5V ± 0.125V tsk(o) nQx Qx nQy Qy Clock Outputs 20% 80% 80% 20% tR tF VSWING tPW tPERIOD tPW tPERIOD odc = x 100% Q0, Q1 nQ0, nQ1 Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD PHASE JITTER OUTPUT SKEW SCOPE Qx nQx LVPECL VEE -1.3V ± 0.165V VCC, VCCO VCCOVCC VCCA VCCA 2.8V±0.04V
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. land pattern must be connected to ground through these vias. Electrically Enhance Leadfame Base Package, Amkor Technology.
IDT™ / ICS™ WCDMA CLOCK GENERATOR/JITTER ATTENUATOR 12 ICS843002BKI-72 REV. A NOVEMBER 21, 2007 ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR VCXO-PLL EXTERNAL COMPONENTS Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (C L ). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal’s load capacitance C L characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (C TUNE If the crystal’s C L is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal’s C L is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE htdiwdnaB) zHM(ycneuqerFlatsyrCR S k( ΩΩΩΩΩ)C S )Fµ(C P )Fµ(R TES k( ΩΩΩΩΩ) )woL(zH57z HM2.915 10 .11 0.08 )diM(zH005z HM2.910 011 .01 000.08 )hgiH(zHk1z HM2.910 011 .01 000.04 CRYSTAL CHARACTERISTICS VCXO CHARACTERISTICS TABLE lobmySr etemaraPm uminiMl acipyTm umixaMs tinU noitarepOfoedoMl atnemadnuF fN ycneuqerF2 .91z HM fT ecnareloTycneuqerF0 2±m pp fS ytilibatSycneuqerF0 2±m pp egnaRerutarepmeTgnitarepO0 4-5 8C ° CL ecnaticapaCdaoL2 1F p CO ecnaticapaCtnuhS4 F p CO/C1 oitaRytiliballuP0 220 42 RSEe cnatsiseRseireStnelaviuqE0 2 Ω leveLevirD1 W m C°52@gnigAr aeyrep3±m pp lobmySr etemaraPl acipyTt inU k OXCV niaGOXCV8 .7V /zHk C WOL_V ecnaticapaCrotcaraVwoL2 F p C HGIH_V ecnaticapaCrotcaraVhgiH8 F p the crystal specification. In either case, the absolute tuning range is reduced. The correct value of C L is dependent on the characteristics of the VCXO. The recommended C L in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows R S , C S and C P values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. LF0 LF1 ISET XTAL_IN XTAL_OUT RS CSCP RSET CTUNE CTUNE 19.2MHz
This section provides information on power dissipation and junction temperature for the ICS843002I-72. Equations and example calculations are also provided. The total power dissipation for the ICS843002I-72 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 140mA = 485.15mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power _MAX (3.465V, with all outputs switching) = 485.1mW + 60mW = 545.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.541W * 37°C/W = 105.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 32-PIN VFQFN, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 7. θ
TABLE 8. PACKAGE DIMENSIONS this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 11 below.
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION
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Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA ICS843002I-72 FEMTOCLOCKS™ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR