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Femtoclock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843002 Data Sheet ©2016 Integrated Device Technology, Inc Revision B January 21, 20161 GENERAL DESCRIPTION The 843002 is a two output LVPECL synthesizer optimized to generate Fibre Channel reference clock frequencies . Using a 26.5625MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and 53.125MHz. The 843002 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The 843002 is packaged in a small 20-pin TSSOP package.
FEATURES
Two 3.3V LVPECL outputs Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz VCO range: 560MHz - 680MHz RMS phase jitter (637kHz - 10MHz): 0.72ps (typical) Typical phase noise at 212.5MHz Phase noise: Offset Noise Power Full 3.3V supply mode Lead-Free package RoHS compliant -30°C to 85°C ambient operating temperature PIN ASSIGNMENT Phase Detector VCO 637.5MHz (w/26.5625MHz Reference) OSC M = 24 (fixed) F_SEL[1:0] 0 0 ÷3 0 1 ÷4 1 0 ÷6 1 1 ÷12 843002 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View BLOCK DIAGRAM FREQUENCY SELECT FUNCTION TABLE F_SEL[1:0] nPLL_SEL TEST_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR nQ0 nQ1 Pulldown Pulldown 26.5625MHz Pulldown Pulldown Pulldown Inputs Output Frequency (MHz) Input Fre- quency (MHz) F_SEL1 F_SEL0 M Divider Value N Divider Value M/N Divider Value 26.5625 0 0 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 0 24 3 8 187.5
843002 Data Sheet
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 2, 20 V CCO Power Output supply pins. 3, 4 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
5 MR Input Pulldown
abled. LVCMOS/LVTTL interface levels. (PLL Bypass). LVCMOS/LVTTL interface levels. CCA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10, 16 V CC Power Core supply pin. 14 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input. source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. EE Power Negative supply pins. 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc Revision B January 21, 20163 TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage nPLL_SEL, nXTAL_SEL, F_SEL0, F_SEL1, MR -0.3 0.8 V TEST_CLK -0.3 1.0 V IIH Input High Current TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, V CC = VIN = 3.63V 150 µA IIL Input Low Current TEST_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, V CC = 3.63V, VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3.3 3.63 V VCCO Output Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 135 mA ICC Core Supply Current 100 mA ICCA Analog Supply Current 15 mA ICCO Output Supply Current 31 mA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CCO - 1.4 V CCO - 0.9 V VOL Output Low Voltage; NOTE 1 V CCO - 2.0 V CCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: See Phase Noise plot.
©2016 Integrated Device Technology, Inc Revision B January 21, 20165 106.25MHz RMS Phase Jitter (Random) 637Khz to 10MHz = 0.84ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M Fibre Channel Jitter Filter Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 106.25MHZ TYPICAL PHASE NOISE AT 53.125MHZ -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 53.125MHz RMS Phase Jitter (Random) 637Khz to 10MHz = 0.97ps (typical) OFFSET FREQUENCY (HZ) 10 100 1k 10k 100k 1M 10M 100M Fibre Channel Jitter Filter Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data dBc Hz NOISE POWER
©2016 Integrated Device Technology, Inc Revision B January 21, 20166 TYPICAL PHASE NOISE AT 212.5MHZ 212.5MHz RMS Phase Jitter (Random) 637Khz to 10MHz = 0.72ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M Fibre Channel Jitter Filter Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M 159.375MHz RMS Phase Jitter (Random) 637Khz to 10MHz = 0.76ps (typical) OFFSET FREQUENCY (HZ) dBc Hz Fibre Channel Jitter Filter Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data➤ NOISE POWER TYPICAL PHASE NOISE AT 159.375MHZ
©2016 Integrated Device Technology, Inc Revision B January 21, 20167 PARAMETER MEASUREMENT INFORMATION RMS PHASE JITTER OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
FIGURE 1. POWER SUPPLY FILTERING recommended only as guidelines. circuit and clock component process variations.
Figure 3. CRYSTAL INPUt INTERFACE and were chosen to minimize the ppm error.
example of LVEPCL termination is shown in this schematic. for optimizing frequency accuracy.
26.5625 MHz
either surface mount HC49S or through-hole HC49 package. board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE shown in this layout example.
This section provides information on power dissipation and junction temperature for the 843002. Equations and example calculations are also provided. The total power dissipation for the 843002 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 135mA = 490mW
- Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.63V, with all outputs switching) = 490mW + 60mW = 550mW 2. Junction Temperature. JJunction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9. PACKAGE DIMENSIONS
TABLE 10. ORDERING INFORMATION
©2016 Integrated Device Technology, Inc Revision B January 21, 201616 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 Added 187.5MHz to the Frequency Selection Function Table. 8/26/04 A T5 4 AC Characteristics Table - corrected typo, f OUT 180.67 min. to 186.67 min. 12/27/04 A T10 Features section - corrected frequency bullet to read “Supports...output frequen- Ordering Information Table - updated table. 2/7/05 B T5 4 AC Characteristics Table - deleted Propagation Delay. 5/6/05 Updated Datasheet Header and Footer. 4/17/13 B T10 Deleted ICS from part numbers where needed. Corrected part number in the header. Ordering Information - Corrected Package information from 8 Lead TSSOP to 20 Lead TSSOP . Added T to tape and reel part number. Updated header and footer. 1/21/16
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters
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