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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843002-01 DATASHEET 843002-01 REVISION B 4/6/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843002-01 is a 2 output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The 843002- 01 uses ICS’ 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 843002-01 is packaged in a small 20-pin TSSOP package.
FEATURES
Two 3.3V LVPECL outputs Selectable crystal oscillator interface or LVCMOS single-ended input Supports the following input frequencies: 156.25MHz, 125MHz and 62.5MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.54ps (typical) Typical phase noise at 156.25MHz Phase noise: Offset Noise Power Full 3.3V supply mode Lead-Free package fully RoHS compliant -30°C to 85°C ambient operating temperature PIN ASSIGNMENT Phase Detector VCO 625MHz (w/25MHz Reference) M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 not used OSC 843002-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View BLOCK DIAGRAM Inputs Output Frequency (25MHz Ref.)F_SEL1 F_SEL0 M Divider Value N Divider Value 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 Not Used Not Used FREQUENCY SELECT FUNCTION TABLE F_SEL[1:0] nPLL_SEL TEST_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR nQO nQ1 Pulldown Pulldown 25MHz nc VCCO nQ0 MR nPLL_SEL nc VCCA F_SEL0 VCC V CCO nQ1 V EE VCC nXTAL_SEL TEST_CLK XTAL_IN XTAL_OUT F_SEL1 Pulldown Pulldown Pulldown
2 REVISION B 4/6/15
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 2, 20 V CCO Power Output supply pins. 3, 4 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
5 MR Input Pulldown
abled. LVCMOS/LVTTL interface levels. (PLL Bypass). LVCMOS/LVTTL interface levels. CCA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10, 16 V CC Power Core supply pin. 14 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input. source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. EE Power Negative supply pins. 18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 2, 20 V CCO Power Output supply pins. NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
3 FemtoClock ® Crystal-to-3.3V LVPECL Frequency Synthesizer TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3.3 3.63 V VCCO Output Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 135 mA ICC Core Supply Current 100 mA ICCA Analog Supply Current 15 mA ICCO Output Supply Current 31 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage nPLL_SEL, nXTAL_SEL, F_SEL0, F_SEL1, MR -0.3 0.8 V TEST_CLK -0.3 1.0 V IIH Input High Current TEST_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = VIN = 3.63V 150 µA IIL Input Low Current TEST_CLK, MR, nPLL_ SEL, nXTAL_SEL VCC = 3.63V, VIN = 0V -5 µA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CCO - 1.4 V CCO - 0.9 V VOL Output Low Voltage; NOTE 1 V CCO - 2.0 V CCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
4 REVISION B 4/6/15
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±10%, TA = -30°C TO 85°C NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 3: Phase jitter is dependent on the input source used. TABLE 4. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal.
5 FemtoClock ® Crystal-to-3.3V LVPECL Frequency Synthesizer OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 125MHZ 125MHz RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.60ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 62.5MHZ 62.5MHz RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.79ps (typical) Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
10 Gigabit Ethernet Filter
Phase Noise Result by adding
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843002-01 DATA SHEET
6 REVISION B 4/6/15
TYPICAL PHASE NOISE AT 156.25MHZ OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Phase Noise Result by adding 156.25MHz RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.54ps (typical)
7 FemtoClock ® Crystal-to-3.3V LVPECL Frequency Synthesizer RMS PHASE JITTER OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843002-01 DATA SHEET
8 REVISION B 4/6/15
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 843002-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC, V CCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01 μF bypass capacitor should be connected to each V CCA. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING recommended only as guidelines. circuit and clock component process variations.
Figure 3. CRYSTAL INPUt INTERFACE and were chosen to minimize the ppm error.
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example of LVEPCL termination is shown in this schematic. for optimizing frequency accuracy. Figure 4B shows an example of 843002-01 P .C. board layout. of either surface mount HC49S or through-hole HC49 package. the board has clean analog power ground plane.
25 MHz
shown in this layout example. TABLE 6. FOOTPRINT TABLE
This section provides information on power dissipation and junction temperature for the 843002-01. Equations and example calculations are also provided. The total power dissipation for the 843002-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 135mA = 490mW
- Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.63V, with all outputs switching) = 490mW + 60mW = 550mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
12 REVISION B 4/6/15
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
14 REVISION B 4/6/15
TABLE 9. PACKAGE DIMENSIONS
TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” to the part number are the Pb-Free confi guration and are RoHS compliant.
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer 843002-01 DATA SHEET
16 REVISION B 4/6/15
Rev Table Page Description of Change Date A T10 Added Lead-Free bullet in Features Section. Added Lead-Free Part/Order Number in Ordering Information table. 1/5/05 A T10 15 Added Lead-Free Marking to Ordering Information Table. 1/11/05 B T5 4 AC Characteristics Table - delete Propagation Delay. 5/6/05 Updated datasheet format. 4/6/15
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