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NG Crystal-to-3.3V LVPECL Clock Generator 843001 DATA SHEET 843001 REVISION B 11/16/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 843001 is a Fibre Channel Clock Generator and a member of the family of high performance devices from IDT. The 843001 uses either a 26.5625MHz or a 23.4375 crystal to synthesize 106.25MHz, 187.5MHz or 212.5MHz, using the FREQ_SEL pin. The 843001 has excellent <1ps phase jitter performance, over the 637kHz – 10MHz integration range. The 843001 is packaged in a small 8-pin TSSOP , making it ideal for use in systems with limited board space.
FEATURES
- One differential 3.3V LVPECL output
- Crystal oscillator interface designed for 23.4375MHz or 26.5625MHz, 18pF parallel resonant crystal
- Selectable 106.25MHz, 187.5MHz or 212.5MHz output frequency
- VCO range: 560MHz - 680MHz
- RMS phase jitter @ 106.255MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.74ps (typical)
- RMS phase noise at 106.25MHz Phase noise: Offset Noise Power
- 3.3V operating supply
- -30°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Inputs Output FrequenciesCrystal Frequency FREQ_SEL 26.5625MHz 0 106.25MHz (Default) 26.5625MHz 1 212.5MHz 23.4375MHz 1 187.5MHz FUNCTION TABLE 843001 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View VCCA VEE XTAL_OUT XTAL_IN VCC nQ0 FREQ_SEL OSC Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. M = ÷24 (fixed) 0÷6 BLOCK DIAGRAM P IN ASSIGNMENT XTAL_IN XTAL_OUT nQ0 FREQ_SEL (Pulldown)
843001 DATA SHEET
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TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 5 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 6, 7 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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TABLE 4. CRYSTAL CHARACTERISTICS tended periods may affect product reliability.
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TABLE 5. AC CHARACTERISTICS, V NOTE 1: Please refer to Phase Noise Plot.
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3.3V LVPECL CLOCK GENERATOR OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 212.5MHZ 212.5MHz RMS Phase Noise Jitter 637K to 10MHz = 0.67ps (typical) Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter TYPICAL PHASE NOISE AT 106.25MHZ 106.25MHz RMS Phase Jitter (Random) 637Khz to 10MHz = 0.74ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Phase Noise Result by adding Fibre Channel Filter to raw data Raw Phase Noise Data Fibre Channel Filter
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR
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OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M TYPICAL PHASE NOISE AT 187.5MHZ 187.5MHz RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.52ps (typ- ical) Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
10 Gigabit Ethernet Filter
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3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER
FEMTOCLOCKS™ CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR
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APPLICATION INFORMATION
FIGURE 2. CRYSTAL INPUt INTERFACE for different board layouts. FIGURE 1. POWER SUPPLY FILTERING
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for optimizing frequency accuracy.
- There should be at least one decoupling capacitor per power pin.
TABLE 6. FOOTPRINT TABLE es shown in this layout example.
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This section provides information on power dissipation and junction temperature for the 843001. Equations and example calculations are also provided. The total power dissipation for the 843001 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V CC_MAX * I EE_MAX = 3.465V * 93mA = 322.2mW
- Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
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- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
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TABLE 8. θ
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TABLE 9. PACKAGE DIMENSIONS
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TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
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3.3V LVPECL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 Corrected block diagram. 6/1/04 B T3A 3 Power Supply DC Characteristics Table- added ICCA spec. 8/23/04 B T10 Added Lead-Free bullet in Features section. Ordering Information Table - added “Lead-Free” part. 12/14/04 “AG” from “..BG”. 12/06/06 Updated data sheet format. 11/16/15
6024 Silver Creek Valley Road
San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.