8430002AYLF | DigiCamel IC Datasheet

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Features

6-Bit Integer and 12-Bit Fractional Feedback Divider
Dual differential 3.3V LVPECL outputs which can be set independently for either 3.3V or 2.5V
2:1 Input Mux: One differential input One crystal oscillator interface
PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL
Output frequency range: 30.625MHz to 640MHz
Crystal input frequency range: 12MHz to 40MHz
VCO range: 490MHz to 650MHz
Parallel or serial interface for programming feedback divider and output dividers
Supply voltage modes: Core/Outputs: 3.3V/3.3V 3.3V/2.5V
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package HiPerClockS™ ICS 13 14 15 16 17 18 19 20 21 22 23 24 NB0 NB1 NB2 OE_REF OEA OEB VCC NA0 NA1 NA2 VEE nc nc XTAL_OUT XTAL_IN nc nc SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUTA nFOUTA VCCO_A FOUTB nFOUTB VCCO_B REF_OUT VCCO_REF nc VEE VCO_SEL nP_LOAD nPCLK PCLK 48 47 46 45 44 43 42 41 40 39 38 37 Pin Assignment ICS8430002

48 Lead LQFP

7mm x 7mm x 1.4mm package body Y Package Top View

ICS8430002AY REVISION C NOVEMBER 12, 2009 2 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Block Diagram ÷ M 1 000 ÷1 001 ÷2 010 ÷3 011 ÷4 100 ÷5 101 ÷6 110 ÷8 111 ÷16 000 ÷1 001 ÷2 010 ÷3 011 ÷4 100 ÷5 101 ÷6 110 ÷8 111 ÷16 OSC VCO FOUTA nFOUTA FOUTB nFOUTB REF_OUT TEST VCCO_REF VCCO_B VCCO_A OEA OEB MR VCO_SEL PCLK nPCLK SEL P[2:0] OE_REF S_LOAD S_DATA S_CLOCK nP_LOAD M5:M0 NA2:NA0 NB2:NB0 XTAL_IN XTAL_OUT Configuration Interface Logic P_DIV Phase Detector Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pullup/Pulldown Pullup Pullup Pullup

ICS8430002AY REVISION C NOVEMBER 12, 2009 3 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Functional Description NOTE: The functional description that follows describes the operation using a 25MHz crystal or clock input. Valid PLL loop divider values for different crystal or clock input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1 and NOTE 2. When a crystal is being used, there is no pre-divider therefore set P = 1 when referencing all following equations on this page. The ICS8430002 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. It has a 2:1 multiplexer from which either a crystal input or a differential input can be selected. An external fundamental-mode quartz crystal can be used as the input to the on-chip crystal oscillator. The range of allowable crystal frequencies is 12MHz to 40MHz. When selected, the crystal frequency is the reference frequency input to the phase detector. The relationship between the VCO frequency, the crystal input frequency and the M divider (M) is as follows: A differential input clock can also be used. (See the Application Information section for Wiring the Differential Input to Accept Single-Ended Levels.) The differential input is followed by a pre-divider that divides down the clock input frequency. This allows an equal or lower reference frequency for the phase detector. See Table 3C for available pre-divider values. The pre-divider value is set through the P[2:0] pins or by using the serial programming interface. The output frequency of the pre-divider is the reference frequency input to the phase detector. The input frequency range of the phase detector is 9MHz to 50MHz. The relationship between the VCO frequency, the clock input frequency, the pre-divider (P) and the M divider (M) is as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. The VCO of the PLL operates over a range of 490MHz to 650MHz. Note that for some values of M (either too high or too low), the PLL will not achieve lock. Using a 25MHz input, the M value integer-only range is shown in Table 3B, Programmable VCO Frequency Table, P = ÷1. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 19.6 ≤ M ≤ 25.6. For different reference frequencies, the range of valid M values may be calculated as follows: The output of the VCO is scaled by output dividers prior to being sent to each of the LVPECL output buffers. The output divider settings and output frequency ranges are shown in table 3D. Combining all the values of input frequency, pre-divider setting, integer and fractional feedback divider settings, and output divider setting, the output frequency may be calculated. The frequency out is defined as follows: The fractional-n M divider is composed of a 6-bit integer portion and a 12-bit fractional portion. The decimal value obtained from these settings can be determined as follows: Where:M INT is the 6-bit integer portion MFRAC is the 12-bit fractional portion For a given required M divider, the value to program into the MFRAC register is calculated by taking the fractional portion and multiplying by 4096. For example, assuming a 25MHz crystal is being used, and the desired VCO frequency is 515.625 (to support ethernet with 64B/66B encoding) the feedback setting required would be 20.625. The integer portion of this number (20) is programed into the MINT register. The fractional portion (0.625) is multiplied by 4096. The result (2560) is programmed into the MFRAC register. The full M divider setting is then: The frequency step size in ppm can be calculated using the following: Substituting the combined equation for the F terms in the step size equation, the equation can be reduced to just the change in M values. Input Min (MHz) Input Max (MHz) Pre-Divider 95 0 ÷ 1 18 100 ÷2 36 200 ÷4 45 250 ÷5 72 400 ÷8 144 800 ÷16 225 800 ÷25 288 800 ÷32 FVCO XTAL M×= FVCO FIN 490MHz FOUT FVCO FIN N-----×== MM INT MFRAC 20 2560 stepsize F0 F1– FIN N-----× stepsize M0 M1–

ICS8430002AY REVISION C NOVEMBER 12, 2009 4 ©2009 Integrated Device Technology, Inc. Which, for these conditions, is a step size of 9.6 ppm. specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. the following order as in the table below. Figure 1. Parallel & Serial Load Operations

00 L O W

10 R e s e r v e d

11 R e s e r v e d

1, 47, 48 P2, P0, P1 Input Pulldown Pre-divider control in put pins. See table 3C. LVCMOS/LVTTL interface levels. 2, 3 NB0, NB1 Input Pullup Determines output divider value as defined in Table 3D, Function Table.

5 OE_REF Input Pulldown

6 OEA Input Pullup

Output enable. Controls enabling and disabling of FOUTA, nFOUTA outputs. compliment output is high. LVCMOS/LVTTL interface levels.

7 OEB Input Pullup

Output enable. Controls enabling and disabling of FOUTB, nFOUTB outputs. compliment output is high. LVCMOS/LVTTL interface levels. 8, 14 V CC Power Core supply pins. 9, 10 NA0, NA1 Input Pullup Determines output divider value as defined in Table 3D, Function Table. 12, 24 V EE Power Negative supply pins. 13 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. nFOUTA Output Differential output pair for the synthesizer. LVPECL interface levels. 17 V CCO_A Power Output supply pin for FO UTA/nFOUTA LVPECL outputs. nFOUTB Output Differential output pair for the synthesizer. LVPECL interface levels. 20 V CCO_B Power Output supply pin for FO UTB/nFOUTB LVPECL outputs. 21 REF_OUT Output Reference clock output. LVCMOS/LVTTL interface levels. 22 V CCO_REF Power Output supply pin for REF_OUT. 35, 36 nc Unused No internal connection.

25 MR Input Pulldown

high. When Logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. edge of S_CLOCK. LVCMOS/LVTTL interface levels.

ICS8430002AY REVISION C NOVEMBER 12, 2009 6 ©2009 Integrated Device Technology, Inc. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 27 S_DATA Input Pulldown Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. 28 S_LOAD Input Pulldown Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. 29 V CCA Power Analog supply pin.

30 SEL Input Pulldown

HIGH. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interface. XTAL_I N is the input, XTAL_OUT is the output. 37 PCLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VCC/2 default when left floating. output divider value. LVCMOS/LVTTL interface levels.

ICS8430002AY REVISION C NOVEMBER 12, 2009 7 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Function Tables Table 3A. Parallel and Serial Mode Function Table NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition Table 3B. Programmable VCO Frequency Function Table, P = ÷1 NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 25MHz. Inputs ConditionsMR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. LHX X L ↑ Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. LHX X ↑ LD a t a Contents of the shift register are passed to the M divider and N output divider. LHX X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input does not affect shift registers. LHX X H ↑ Data S_DATA passed directly to M divider as it is clocked. VCO Frequency (MHz) M Divide 32 16 8 4 2 1 M5 M4 M3 M2 M1 M0 5 0 0 2 0 010100 5 5 0 2 2 010110 6 2 5 2 5 011001

ICS8430002AY REVISION C NOVEMBER 12, 2009 8 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Table 3C. Programmable Pre Divider Function Table Table 3D. Programmable Output Divider Function Table NOTE: “x” denotes Bank A or Bank B. Inputs Pre Divider ValueP2 P1 P0 0 0 0 1 (default) 001 2 010 4 011 8 100 1 6 101 3 2 110 5 111 2 5 Inputs N Divider Value Output Frequency (MHz) Nx2 Nx1 Nx0 Minimum Maximum 0 0 0 1 490 640 0 0 1 2 245 325 0 1 0 3 163.33 216.67 0 1 1 4 (default) 122.5 162.5 100 5 9 8 1 3 0 1 0 1 6 81.67 108.33 1 1 0 8 61.25 81.25 1 1 1 16 30.625 40.625

ICS8430002AY REVISION C NOVEMBER 12, 2009 9 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO_A = VCCO_B = VCCO_REF = 3.3V±5% or 2.5V±5%, VEE =0V, TA = 0°C to 70°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) 50mA 100mA -0.5V to VCCO_REF + 0.5V Package Thermal Impedance, θJA 65.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage V CC – 0.13 3.3 V CC V VCCO_A, VCCO_B, VCCO_REF Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IEE Power Supply Current 182 mA ICCA Analog Supply Current 13 mA

ICS8430002AY REVISION C NOVEMBER 12, 2009 10 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VCCO_REF = 3.3V±5% or 2.5V±5%, VEE =0V, TA = 0°C to 70°C NOTE 1: Output terminated with 50Ω to VCCO_REF/2. See Parameter Measurement Information section. Load Test Circuit diagrams. NOTE 2: Output terminated with 50Ω to VCC/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4C. LVPECL DC Characteristics, VCC =3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% or 2.5V±5%,VEE =0V, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50Ω to VCCO_A, _B – 2V. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage V CC = 3.3V 2 V CC + 0.3 V VIL Input Low Voltage V CC = 3.3V -0.3 0.8 V IIH Input High Current P[2:0], NB2, NA2, MR, OE_REF, SEL, M[4:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD V CC = VIN = 3.465V 150 µA VCO_SEL, OEA, OEB VCC = VIN = 3.465V 5 µA IIL Input Low Current P[2:0], NB2, NA2, MR, OE_REF, SEL, M[4:0], S_CLOCK, S_DATA, S_LOAD, nP_LOAD V CC = 3.465V, VIN = 0V -5 µA VCO_SEL, OEA, OEB VCC = 3.465V, VIN = 0V -150 µA VOH Output High Voltage REF_OUT; NOTE 1 VCCO_REF = 3.3V±% 2.6 V VCCO_REF = 2.5V±5% 1.8 V TEST; NOTE 2 V CC = 3.3V±% 2.6 V VOL Output Low Voltage REF_OUT; NOTE 1 V CCO_REF = 3.3V±5% or 2.5V±5% 0.5 V TEST; NOTE 2 V CC = 3.3V±% 0.5 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current PCLK/nPCLK V CC = VIN = 3.465V 150 µA IIL Input Low Current PCLK V CC = 3.465V, VIN = 0V -5 µA nPCLK V CC = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.3 1.0 V VCMR Common Mode Input Voltage; NOTE 1, 2 V EE + 1.5 V CC V VOH Output High Voltage; NOTE 3 V CCO – 1.4 V CCO – 0.9 V VOL Output Low Voltage; NOTE 3 V CCO – 2.0 V CCO – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

ICS8430002AY REVISION C NOVEMBER 12, 2009 11 ©2009 Integrated Device Technology, Inc. Table 5. Input Frequency Characteristics, TA = 0°C to 70°C M = MINT + MCALC. The M value must be set for the VCO range to operate within the 490MHz - 650MHz range. used, adjust MFRAC to adjust the value of M according to the instructions on page 3. has a range of 10 ≤ MINT ≤ 13 assuming the MFRAC is used to meet the requirement 10 ≤ M ≤ 13. MINT must not be set lower than 10. Table 6. Crystal Characteristics

ICS8430002AY REVISION C NOVEMBER 12, 2009 12 ©2009 Integrated Device Technology, Inc. Table 7. AC Characteristics, VCC = VCCO_A = VCCO_B = VCCO_REF = 3.3V±5% or 2.5V±5%, VEE =0V, TA = 0°C to 70°C been reached under these conditions. NOTE: See Parameter Measurement Information section. NOTE 1:This parameter is defined in accordance with JEDEC Standard 65.

ICS8430002AY REVISION C NOVEMBER 12, 2009 13 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Parameter Measurement Information 3.3/3.3V LVPECL Output Load AC Test Circuit 3.3/3.3V LVCMOS Output Load AC Test Circuit Differential Input Level 3.3V/2.5V LVPECL Output Load AC Test Circuit 3.3/2.5V LVCMOS Output Load AC Test Circuit Period Jitter SCOPE Qx nQx LVPECL VEE VCC, -1.3V±0.165V- VCCO_A, VCCO_B VCCA SCOPE QxLVCMOS GND 1.65V±5% -1.65V±5% 1.65V±5% VCC, VCCA VCCO_REF VCC VEE VCMR Cross Points VPP PCLK nPCLK SCOPEQx nQx LVPECL VEE -0.5V±0.125V VCC 2.8V±0.04V VCCO_A, 2.8V±0.04V VCCA VCCO_B SCOPE Qx GND LVCMOS 1.25V±5% -1.25V±5% 2.05V±5% 2.05V±5% VCC, VCCA VCCO_REF VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram

ICS8430002AY REVISION C NOVEMBER 12, 2009 14 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Parameter Measurement Information, continued Cycle-to-Cycle Jitter LVPECL Output Duty Cycle/Pulse Width/Period LVPECL Output Skew LVPECL Output Rise/Fall Time ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

odc = x 100% FOUTx FOUTy nFOUTx nFOUTy tsk(o) 20% 80% 80% 20% tR tF VSWING nFOUTx FOUTx

ICS8430002AY REVISION C NOVEMBER 12, 2009 18 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. PCLK/nPCLK Inputs For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: TEST Output The unused TEST output can be left floating. There should be no trace attached. LVCMOS Output All unused LVCMOS output can be left floating. There should be no trace attached. LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 7A and 7B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 7A. 3.3V LVPECL Output Termination Figure 7B. 3. 3V LVPECL Output Termination 3.3V VCC - 2V 50Ω 50Ω RTT Z o = 50Ω Zo = 50Ω RTT = * Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V LVPECL Input 84Ω 84Ω 3.3VR3 125Ω 125Ω Zo = 50Ω Zo = 50ΩLVPECL Input 3.3V 3.3V

ICS8430002AY REVISION C NOVEMBER 12, 2009 21 ©2009 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8430002. Equations and example calculations are also provided. The total power dissipation for the ICS8430002 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. 125°C ensures that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 65.7°C/W per Table 8 below. Table 8. Thermal Resistance θJA for 48 Lead TQFP, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 10. Figure 10. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Ordering Information

Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS8430002AY REVISION C NOVEMBER 12, 2009 26 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER Revision History Sheet Rev Table Page Description of Change Date B T1 5 Pin 5, 6, 7 added to descriptions. Changed max VCO from 640MHz to 650MHz throughout the datasheet. 5/5/09 CT 1 T3D Block Diagram - changed OE_A, OE_B to OEA, OEB. Figure 1, Parallel & Serial Load Operations - correct M[11:0] to M[5:0]. Pin Descriptions Table - changed OE_A, OE_B to OEA, OEB. Programmable Output Divider Table - corrected Output Frequency max. column. Input Frequency Characteristics - corrected equations in NOTE 1 and NOTE 2. 8/24/09 C 1 General Description - deleted the word possible at the end of the first sentence. 11/12/09

ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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Product Information

8430002AYLF specifications and overview.

Summary

High-Performance Fractional-N Frequency Synthesizer

Description

High-Performance Fractional-N Frequency Synthesizer

Source title 8430002AYLF Datasheet(PDF) - Integrated Device Technology

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