842S104E RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Integrated Device Technology
- PDF pages: 23
Technical content
Features
- Four differential HSTL output pairs
- Crystal oscillator interface: 25MHz
- Output frequency: 100MHz or 200MHz
- RMS phase jitter @ 200MHz (12kHz – 20MHz): 1.229ps (typical)
- Cycle-to-cycle jitter: 25ps (maximum)
- I2C support with readback capabilities up to 400kHz
- Spread Spectrum for electromagnetic interference (EMI) reduction
- 3.3V core/1.5V to 2.0V output operating supply
- 0°C to 70°C ambient operating temperature
- Available lead-free (RoHS 6) package
- PCI Express Gen2 Jitter Compliant HiPerClockS™ OSC PLL Divider Network I2C Logic SDATA SCLK Pullup Pullup SRCT[1:4] SRCC[1:4] 25MHz XTAL_IN XTAL_OUT 842S104E 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View VSS VDD VDDO VSS SRCC1 SRCT1 SRCC2 SRCT2 VSS SRCC3 SRCT3 nc SRCC4 SRCT4 SDATA SCLK nc XTAL_OUT XTAL_IN VDDO VDD VDDA VSS VSS Pin AssignmentBlock Diagram Crystal-to-HSTL, 100MHz/ 200MHz PCI Express™ Clock Synthesizer 842S104E Datasheet
Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 SRCT3, SRCC3 Output Differential ou tput pair. HSTL interface levels. 11, 13, 16 VSS Power Power supply ground. 4, 22 V DDO Power Output power supply pins. 5, 6 SRCT2, SRCC2 Output Differential ou tput pair. HSTL interface levels. 7, 8 SRCT1, SRCC1 Output Differential ou tput pair. HSTL interface levels. 10, 17 V DD Power Core supply pins. 12, 15 nc Unused No connect. 14 V DDA Power Analog supply for PLL. 18, 19 XTAL_IN, XTAL_OUT Input Crystal oscillator interfac e. XTAL_IN is the input. XTAL_OUT is the output. 20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. Open drain. LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output Differential ou tput pair. HSTL interface levels.
3©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default setting upon power-up, therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (mo st significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operat ions, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Table 3B. Block Read and Block Write Protocol Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation. 6:5 Chip select address, se t to “00” to access device. 4:0 Byte offset for byte read or byte write operation. For bl ock read or block write operations, these bits must be “00000”. Bit Description = Block Writ e Bit Description = Block Read 1S t a r t 1S t a r t 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9W r i t e 9W r i t e
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code - 8 bits 11:18 Command Code - 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte Count - 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address - 7 bits
29:36 Data byte 1 - 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits
46 Acknowledge from slave 38 Acknowledge
Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits Data Byte N - 8 bits 47 Acknowledge Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits Stop 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge
4©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Table 3C. Byte Read and Byte Write Protocol Bit Description = Byte Write Bit Description = Byte Read
1 Start 1 Start
2:8 Slave address - 7 bits 2:8 Slave address - 7 bits
9 Write 9 Write
11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 20:27 Data Byte - 8 bits 20 Repeat start
29 Stop 28 Read
29 Acknowledge from slave
30:37 Data from slave - 8 bits
38 Not Acknowledge
39 Stop
5©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Control Registers Table 3D. Byte 0: Control Register 0 NOTE: @PUP denotes at power-up. Table 3E. Byte 1: Control Register 1 Table 3F. Byte 2: Control Register 2 Table 3G. Byte 3:Control Register 3 Bit @Pup Name Description 7 0 Reserved Reserved 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z) 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z) 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved
20 S R C
0 = Spread Off, 1 = Spread On 1 1 Reserved Reserved
01 F O U T C T L
0 = 100MHz 1 = 200MHz Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved
6©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Table 3H. Byte 4: Control Register 4 Table 3I. Byte 5: Control Register 5 Table 3J. Byte 6: Control Register 6 NOTE: @PUP denotes at power-up. Table 3K. Byte 7: Control Register 7 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N
60 T E S T _ M O D E
0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0
7©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V to 2.0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V to 2.0V, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 77.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.25 3.3 V DD V VDDO Output Supply Voltage 1.5 2.0 V IDD Power Supply Current 106 mA IDDA Analog Supply Current 25 mA IDDO Output Supply Current 7m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SDATA, SCLK V DD = VIN = 3.465V 10 µA IIL Input Low Current SDATA, SCLK V DD = 3.465V, VIN = 0V -150 µA
NOTE 1: Outputs terminated with 50 to GND. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V to 2.0V, TA = 0°C to 70°C has been reached under these conditions. Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE: 2: This parameter is guaranteed by characterization. Not tested in production. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
10©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Typical Phase Noise at 200MHz Noise Power dBc Hz Offset Frequency (Hz)
11©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Parameter Measurement Information 3.3V HSTL Output Load AC Test Circuit Cycle-to-Cycle Jitter RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE HSTL Qx nQx GND VDD 3.3V±5% VDDO VDDA 3.3V±5% 1.5V to 2.0V SRCT[1:4] tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
SRCC[1:4] SRCT[1:4] SRCC[1:4]
Figure 1. Power Supply Filtering should either be left floating or terminated.
Figure 6 shows an example of 842S104E application schematic. In this example, the device is operated at V DD = 3.3V and V DDO = 1.8V. examples are shown in this schematic. The decoupling capacitor should be located as close as possible to the power pin. Figure 6. 842S104E Schematic Example
24 SRCT3
16©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet PCI Express Application Note PCI Express jitter analysis me thodology mode ls the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is pr ovided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transf er function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.
This section provides information on power dissipation and junction temperature for the 842S104E. Equations and example calculations are also provided. The total power dissipation for the 842S104E is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 77.5°C/W per Table 7 below. Table 7. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the HSTL output pair. HSTL output driver circuit and termination are shown in Figure 7. Figure 7. HSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 8. JA vs. Air Flow Table for a 24 Lead TSSOP
20©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet
Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
21©2016 Integrated Device Technology, Inc January 4, 2016 842S104E Datasheet Revision History Sheet Revision Date Table Page Description of Change January 4, 2016 Updated datasheet header/footer. Deleted “ICS” prefix from part number.
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA www.IDT.com 842S104E Datasheet
© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.