842S104CGLF | DigiCamel IC Datasheet

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ICS842S104 IDT | Alldatasheet

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Features

Four differential HSTL output pairs
Crystal oscillator interface: 25MHz
Output frequency: 100MHz or 200MHz
RMS phase jitter @ 200MHz (12kHz – 20MHz): 1.27ps (typical)
Cycle-to-cycle jitter: 25ps (maximum)
I2C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V core/1.5V to 2.0V output operating supply
0°C to 70°C ambient operating temperature
Available lead-free (RoHS 6) package
PCI Express Gen2 Jitter Compliant HiPerClockS™ OSC PLL Divider Network I2C Logic SDATA SCLK Pullup Pullup SRCT[1:4] SRCC[1:4] 25MHz XTAL_IN XTAL_OUT ICS842S104 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View VSS VDD VDDO VSS SRCC1 SRCT1 SRCC2 SRCT2 VSS SRCC3 SRCT3 nc SRCC4 SRCT4 SDATA SCLK nc XTAL_OUT XTAL_IN VDDO VDD VDDA VSS VSS Pin AssignmentBlock Diagram

ICS842S104CG REVISION A MARCH 17, 2010 2 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 SRCT3, SRCC3 Output Differential ou tput pair. HSTL interface levels. 11, 13, 16 VSS Power Power supply ground. 4, 22 V DDO Power Output power supply pins. 5, 6 SRCT2, SRCC2 Output Differential ou tput pair. HSTL interface levels. 7, 8 SRCT1, SRCC1 Output Differential ou tput pair. HSTL interface levels. 10, 17 V DD Power Core supply pins. 12, 15 nc Unused No connect. 14 V DDA Power Analog supply for PLL. 18, 19 XTAL_IN, XTAL_OUT Input Crystal oscillator interfac e. XTAL_IN is the input. XTAL_OUT is the output. 20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output Differential ou tput pair. HSTL interface levels.

ICS842S104CG REVISION A MARCH 17, 2010 3 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation. 6:5 Chip select address, se t to “00” to access device. 4:0 Byte offset for byte read or byte write operation. For bl ock read or block write operations, these bits must be “00000”.

ICS842S104CG REVISION A MARCH 17, 2010 4 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Table 3B. Block Read and Block Write Protocol Table 3C. Byte Read and Byte Write Protocol Bit Description = Block Writ e Bit Description = Block Read 1S t a r t 1S t a r t 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9W r i t e 9W r i t e

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Byte Count - 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address - 7 bits

29:36 Data byte 1 - 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits

46 Acknowledge from slave 38 Acknowledge

Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits Data Byte N - 8 bits 47 Acknowledge Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits Stop 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge Bit Description = Byte Write Bit Description = Byte Read

1 Start 1 Start

2:8 Slave address - 7 bits 2:8 Slave address - 7 bits

9 Write 9 Write

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 20:27 Data Byte - 8 bits 20 Repeat start

29 Stop 28 Read

29 Acknowledge from slave

30:37 Data from slave - 8 bits

38 Not Acknowledge

39 Stop

ICS842S104CG REVISION A MARCH 17, 2010 5 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Control Registers Table 3D. Byte 0: Control Register 0 Table 3E. Byte 1: Control Register 1 Table 3F. Byte 2: Control Register 2 Table 3G. Byte 3:Control Register 3 Table 3H. Byte 4: Control Register 4 Table 3I. Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z) 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z) 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved

20 S R C

0 = Spread Off, 1 = Spread On 1 1 Reserved Reserved 0 1 FOUTCTL Output Frequency Control 0 = 100MHz 1 = 200MHz Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved

ICS842S104CG REVISION A MARCH 17, 2010 6 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Table 3J. Byte 6: Control Register 6 Table 3K. Byte 7: Control Register 7 Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N 6 0 TEST_MODE TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0

ICS842S104CG REVISION A MARCH 17, 2010 7 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V to 2.0V, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 4C. HSTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.5V to 2.0V, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50Ω to GND. NOTE 2: Defined with respect to output voltage swing at a given condition. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 77.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.21 3.3 V DD V VDDO Output Supply Voltage 1.5 2.0 V IDD Power Supply Current 106 mA IDDA Analog Supply Current 21 mA IDDO Output Supply Current 7m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SDATA, SCLK V DD = VIN = 3.465V 10 µA IIL Input Low Current SDATA, SCLK V DD = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 0.9 1.2 V VOL Output Low Voltage; NOTE 1 0 0.4 V VOX Output Crossover Voltage; NOTE 2 40% x (VOH - VOL) + VOL 65% x (VOH - VOL) + VOL % VSWING Peak-to-Peak Output Voltage Swing 0.6 1.1 V

ICS842S104CG REVISION A MARCH 17, 2010 8 ©2010 Integrated Device Technology, Inc. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

ICS842S104CG REVISION A MARCH 17, 2010 9 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Typical Phase Noise at 200MHz Noise Power dBc Hz Offset Frequency (Hz)

ICS842S104CG REVISION A MARCH 17, 2010 10 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER Parameter Measurement Information 3.3V HSTL Output Load AC Test Circuit Cycle-to-Cycle Jitter RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE HSTL Qx nQx GND VDD 3.3V±5% VDDO VDDA 3.3V±5% 1.5V to 2.0V SRCT(1:4) ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

SRCC(1:4) Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power tPW tPERIOD tPW tPERIOD odc = x 100% SRCT(1:4) SRCC(1:4)

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS842S104 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering should either be left floating or terminated.

ICS842S104CG REVISION A MARCH 17, 2010 14 ©2010 Integrated Device Technology, Inc. this example, the device is operated at VDD = 3.3V and VDDO = 1.8V. located as close as possible to the power pin. Figure 5. ICS842S104 Schematic Example

24 SRCT3

ICS842S104CG REVISION A MARCH 17, 2010 15 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as well as the overall transfer function Ht. The respective -3 dB pole frequencies for each transfer function are labeled as F1 for transfer function H1, F2 for H2, and F3 for H3. For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. t s() H3 s() H1 s() H2 s(–[×= s) Xs() H3 s()× H1 s() H2(–[×=

ICS842S104CG REVISION A MARCH 17, 2010 16 ©2010 Integrated Device Technology, Inc. ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER PCIe Gen 1 Magnitude of Transfer Function PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function -60 -50 -40 -30 -20 -10 Frequency (Hz) Mag (dB) Magnitude of Transfer Functions - PCIe Gen 1 F1: 2.2e+007 F2: 1.5e+006 F3: 1.5e+006 Ht=(H1-H2)*H3 -60 -50 -40 -30 -20 -10 Frequency (Hz) Mag (dB) Magnitude of Transfer Functions - PCIe Gen 2A F1: 1.6e+007 F2: 5.0e+006 F3: 1.0e+006 Ht=(H1-H2)*H3 -60 -50 -40 -30 -20 -10 Frequency (Hz) Mag (dB) Magnitude of Transfer Functions - PCIe Gen 2B F1: 1.6e+007 F2: 8.0e+006 F3: 1.0e+006 Ht=(H1-H2)*H3

ICS842S104CG REVISION A MARCH 17, 2010 17 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS842S104. Equations and example calculations are also provided. The total power dissipation for the ICS842S104 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. 125°C ensures that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 77.5°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the HSTL output pair. HSTL output driver circuit and termination are shown in Figure 6. Figure 6. HSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS842S104 Data Sheet CRYSTAL-TO- HSTL 100 MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

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Product Information

842S104CGLF specifications and overview.

Summary

Crystal-to-HSTL 100MHz / 200MHz PCI Express??Clock Synthesizer

Description

Crystal-to-HSTL 100MHz / 200MHz PCI Express??Clock Synthesizer

Source title 842S104CGLF Datasheet(PDF) - Integrated Device Technology

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