8422002I-07 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Integrated Device Technology
- PDF pages: 19
Technical content
Features
- Two LVHSTL outputs (VOH_max = 1.2V)
- Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
- Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
- VCO range: 560MHz - 680MHz
- RMS phase jitter @ 212.5MHz, using a 25MHz crystal (637kHz - 10MHz): 0.59ps (typical) design target
- Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package Frequency Select Function Table Inputs N Div. Value M/N Div. Value Output Frequency (MHz)Input Frequency (MHz) F_SEL1 F_SEL0 M Div. Value 26.5625 0 (default) 0 (default) 24 3 8 212.5 26.5625 0 1 24 4 6 159.375 26.5625 1 0 24 6 4 106.25 26.5625 1 1 24 12 2 53.125 23.4375 0 (default) 0 (default) 24 3 8 187.5 F_SEL0 VDDA nc nPLL_SEL MR nQ0 VDDO nc VDD VDDO nQ1 GND VDD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 422002I-07 20-Lead TSSOP, EPad 4.4mm x 6.5mm x 0.90mm package body G Package Top View Pin AssignmentBlock Diagram Phase Detector M = 24 (fixed) F_SEL[1:0] 0 0 ÷3 (default) 0 1 ÷4 1 0 ÷6 1 1 ÷12 OSC nQ0 nQ1 F_SEL[1:0] nPLL_SEL REF_CLK nXTAL_SEL XTAL_OUT XTAL_IN MR Pulldown Pulldown Pulldown 26.5625MHz Pulldown Pulldown 8422002I-07 Data Sheet Femtoclock™ Crystal-To-LVHSTL Frequency Synthesizer
Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 20 V DDO Power Output supply pins. 3, 4 Q0, nQ0 Output Differential outp ut pair. LVHSTL interface levels.
5 MR Input Pulldown
enabled. LVCMOS/LVTTL interface levels. selected reference clock is routed directly to the output dividers. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10, 16 V DD Power Core supply pins. 14 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. 18, 19 nQ1, Q1 Output Differential outp ut pair. LVHSTL interface levels.
3©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.10 3.3 V DD V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Core Supply Current 112 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current No Load 1 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.10 2.5 V DD V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Core Supply Current 106 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current No Load 1 mA
NOTE 1: Outputs termination with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. NOTE 1: Outputs termination with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 4. Crystal Characteristics
5©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet Table 5A. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Table 5B. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Parameter Symbol Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 35 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 212.5MHz, (637kHz – 10MHz) 0.59 ps 187.5MHz, (637kHz – 10MHz) 0.53 ps 159.375MHz, (637kHz – 10MHz) 0.56 ps 106.25MHz, (1.875MHz – 20MHz) 0.56 ps 53.125MHz, (637kHz – 10MHz) 0.66 ps t R / tF Output Rise/Fall Time 20% to 80% 275 875 ps odc Output Duty Cycle N 34 8 5 2 % N = 3 40 60 % Parameter Symbol Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 186.67 226.66 MHz F_SEL[1:0] = 01 140 170 MHz F_SEL[1:0] = 10 93.33 113.33 MHz F_SEL[1:0] = 11 46.67 56.66 MHz tsk(o) Output Skew; NOTE 1, 2 35 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 212.5MHz, (637kHz – 10MHz) 0.60 ps 187.5MHz, (637kHz – 10MHz) 0.72 ps 159.375MHz, (637kHz – 10MHz) 0.64 ps 106.25MHz, (1.875MHz – 20MHz) 0.55 ps 53.125MHz, (637kHz – 10MHz) 0.68 ps t R / tF Output Rise/Fall Time 20% to 80% 250 650 ps odc Output Duty Cycle N 34 8 5 2 % N = 3 40 60 %
6©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet Typical Phase Noise at 212.5MHz (VDD = 3.3V, VDDO = 1.8V) Typical Phase Noise at 106.25MHz (VDD = 3.3V, VDDO = 1.8V) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 212.5MHz RMS Phase Jitter (Random) 637kHz to 10MHz = 0.59ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Fibre Channel Filter Phase Noise Result by adding a Fibre Channel filter to raw data Raw Phase Noise Data 106.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.56ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
7©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet Parameter Measurement Information 3.3V/1.8V Output Load AC Test Circuit Output Skew Output Rise/Fall Time 2.5V/1.8V Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx LVHSTL GND 3.3V±5% 1.8V±0.2V VDDA VDDO VDD 3.3V±5% nQx Qx nQy Qy Q0, Q1 nQ0, nQ1 SCOPE Qx nQx LVHSTL GND VDD VDDA VDDO 2.5V±5% 1.8V±0.2V 2.5V±5% Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power Q0, Q1 nQ0, nQ1
8©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The 8422002I-07 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering tied from XTAL_IN to ground. a 1k resistor can be tied from the REF_CLK to ground. pair should either be left floating or terminated.
of pad pattern for the leads to avoid any shorts. Figure 4. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
This section provides information on power dissipation and junction temperature for the 8422002I-07. Equations and example calculations are also provided. The total power dissipation for the 8422002I-07 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Table 6. Thermal Resistance JA for 20 Lead TSSOP, EPad Forced Convection
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 6. Figure 6. LVHSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP, EPad
15©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP, EPad Table 8. Package Dimensions for 20 Lead TSSOP, EPad Reference Document: JEDEC Publication 95, MO-153 All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.10 A1 0.05 0.15 A2 0.85 0.95 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.50 0.70 P 4.2 P1 3.0 0° 8° aaa 0.076 bbb 0.10
16©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet
Ordering Information
Table 9. Ordering Information
17©2016 Integrated Device Technology, Inc Revision A January 29, 2016 8422002I-07 Data Sheet
Revision History
Revision Date Description of Change January 28,2016 ▪ Removed ICS from the part numbers where needed. ▪ General Description - removed the ICS chip and HiPerClockS. ▪ Features section - remove reference to leaded package. ▪ Ordering Information - removed quantity from tape and reel. Deleted LF note below table. ▪ Updated header and footer.
DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2016 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA www.IDT.com 8422002I-07 Data Sheet
© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.