ICS8422002I-01 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Two LVHSTL outputs (VOHmax = 1.2V)
  • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
  • Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz
  • VCO range: 560MHz - 680MHz
  • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical)
  • Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V
  • -40°C to 85°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment ICS422002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View HiPerClockS™ ICS F_SEL0 VDDA nc nPLL_SEL MR nQ0 VDDO nc VDD VDDO nQ1 GND VDD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 1 1 Phase Detector VCO M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 0 1 ÷5 1 0 ÷10 1 1 Not Used OSC nQ0 nQ1 F_SEL[1:0] nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR Pulldown Pulldown Pulldown Pulldown Pulldown 25MHz The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 2, 20 V DDO Power Output supply pins. 3, 4 Q0, nQ0 Output Differential output pair. LVHSTL interface levels.

5 MR Input Pulldown

enabled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 10, 16 V DD Power Core supply pins. 14 REF_CLK Input Pulldown Single-ended reference cl ock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. 18, 19 nQ1, Q1 Output Differential out put pair. LVHSTL interface levels.

FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 3 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Table 3B. Power Supply DC Characteristics, VDD = VDDA = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Core Supply Current 90 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 0 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Core Supply Current 80 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 0 mA

NOTE 1: Outputs termination with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. NOTE 1: Outputs termination with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 4. Crystal Characteristics

FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 5 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 Table 5A. AC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Table 5B. AC Characteristics, VDD = VDDA = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot. Parameter Symbol Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 TBD ps tjit() RMS Phase Jitter (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.44 ps 125MHz, (1.875MHz – 20MHz) 0.48 ps 62.5MHz, (1.875MHz – 20MHz) 0.49 ps t R / tF Output Rise/Fall Time 20% to 80% 410 ps odc Output Duty Cycle 50 % Parameter Symbol Test Conditions Minimum Typical Maximum Units fOUT Output Frequency F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 2 TBD ps tjit() RMS Phase Jitter (Random); NOTE 3 156.25MHz, (1.875MHz – 20MHz) 0.41 ps 125MHz, (1.875MHz – 20MHz) 0.49 ps 62.5MHz, (1.875MHz – 20MHz) 0.50 ps t R / tF Output Rise/Fall Time 20% to 80% 380 ps odc Output Duty Cycle 50 %

FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 6 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 Typical Phase Noise at 156.25MHz Ethernet Filter Phase Noise Result by adding an Ethernet filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) Noise Power dBc Hz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz)

FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 7 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007 Parameter Measurement Information 3.3V/1.8V Output Load AC Test Circuit Output Skew Output Rise/Fall Time 2.5V/1.8V Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx LVHSTL GND 3.3V±5% 1.8V±0.2V VDDA VDDO VDD, nQx Qx nQy Qy tsk(o) Clock Outputs 20% 80% 80% 20% tR tF VSWING SCOPE Qx nQx LVHSTL GND VDD, VDDA VDDO 2.5V±5% 1.8V±0.2V Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power Q0, Q1 nQ0, nQ1 tPW tPERIOD tPW tPERIOD odc = x 100%

FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 8 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8422002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering protection. A 1kΩ resistor can be used. a 1kΩ resistor can be tied from the REF_CLK to ground. pair should either be left floating or terminated.

This section provides information on power dissipation and junction temperature for the ICS8422002I-01. Equations and example calculations are also provided. The total power dissipation for the ICS8422002I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 5. Figure 5. LVHSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP

FEMTOCLOCKS™ CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER PRELIMINARY IDT™ / ICS™ LVHSTL FREQUENCY SYNTHESIZER 14 ICS8422002AGI-01 REV. C NOVEMBER 1, 2007

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

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