8421002I-01

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8421002I-01 REVISION B 8/14/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 8421002I-01 is a 2 output HSTL Synthesizer optimized to generate Ethernet reference clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The 8421002I-01 uses IDT’s 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 8421002I-01 is packaged in a small 20-pin TSSOP package.

FEATURES

 Two HSTL outputs (VOHmax = 1.5V) Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input  Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz  VCO range: 560MHz - 680MHz  RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical)  Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) compliant package 1 1 Phase Detector VCO M = 25 (fixed) F_SEL[1:0] 0 0 ÷4 (default) 0 1 ÷5 1 0 ÷10 1 1 Not Used OSC 8421002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View BLOCK DIAGRAM Output Frequency (25MHz Ref.)F_SEL1 F_SEL0 M Divider Value N Divider Value 0 0 25 4 156.25 0 1 25 5 125 1 0 25 10 62.5 1 1 not used not used FREQUENCY SELECT FUNCTION TABLE F_SEL[1:0] nPLL_SEL REF_CLK XTAL_IN XTAL_OUT nXTAL_SEL MR nQ0 nQ1 Pulldown Pulldown 25MHz Pulldown Pulldown Pulldown nc VDDO nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD V DDO nQ1 GND V DD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1 PIN ASSIGNMENT

2 REVISION B 8/14/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 3, 4 Q0, nQ0 Ouput Differential output pair. HSTL interface levels.

5 MR Input Pulldown

abled. LVCMOS/LVTTL interface levels. Bypass). LVCMOS/LVTTL interface levels. F_SEL1 Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. 14 REF_CLK Input Pulldown LVCMOS/LVTTL reference clock input. source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. 17 GND Power Power supply ground. 18, 19 nQ1, Q1 Output Differential output pair. HSTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 FEMTOCLOCKS™ CRYSTAL-TO-HSTL

Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA 73.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDA = 3.3V±5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, V DD = V DDA DDO = 1.8V±0.2V, TA = -40°C TO 85°C TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDA = 2.5V±5%, V DDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDA Analog Supply Voltage 3.135 3.3 3.465 V V DDO Output Supply Voltage 1.6 1.8 2.0 V I DD Power Supply Current 110 mA I DDA Analog Supply Current 12 mA I DDO Output Supply Current No Load 0 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 2.375 2.5 2.625 V V DDA Analog Supply Voltage 2.375 2.5 2.625 V V DDO Output Supply Voltage 1.6 1.8 2.0 V I DD Power Supply Current 96 mA I DDA Analog Supply Current 12 mA I DDO Output Supply Current No Load 0 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage V DD = 3.3V 2 V DD + 0.3 V V DD = 2.5V 1.7 V DD + 0.3 V V IL Input Low Voltage V DD = 3.3V -0.3 0.8 V V DD = 2.5V -0.3 0.7 V I IH Input High Current REF_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL V DD = V IN = 3.465V or 2.5V 150 µA I IL Input Low Current REF_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL V DD = 3.465V or 2.5V, V IN = 0V -150 µA

4 REVISION B 8/14/15

TABLE 4. CRYSTAL CHARACTERISTICS NOTE 1: Outputs terminated with 50Ω to ground. NOTE 2: Defi ned with respect to output voltage swing at a given condition. NOTE 1: Outputs terminated with 50Ω to ground. NOTE 2: Defi ned with respect to output voltage swing at a given condition. NOTE: Characterized using an 18pF parallel resonant crystal.

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TABLE 5A. AC CHARACTERISTICS, V DD = V DDA = 3.3V±5%,V DDO = 1.8V±0.2V, TA = -40°C TO 85°C TABLE 5B. AC CHARACTERISTICS, V DD = V DDA = 2.5V±5%,V DDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 3 20 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 156.25MHz, (1.875MHz - 20MHz) 0.44 ps 125MHz, (1.875MHz - 20MHz) 0.48 ps 62.5MHz,(1.875MHz - 20MHz) 0.49 ps t R / t F Output Rise/Fall Time 20% to 80% 215 815 ps odc Output Duty Cycle 48 52 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO /2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency F_SEL[1:0] = 00 140 170 MHz F_SEL[1:0] = 01 112 136 MHz F_SEL[1:0] = 10 56 68 MHz tsk(o) Output Skew; NOTE 1, 3 20 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2 156.25MHz, (1.875MHz - 20MHz) 0.41 ps 125MHz, (1.875MHz - 20MHz) 0.49 ps 62.5MHz,(1.875MHz - 20MHz) 0.50 ps t R / t F Output Rise/Fall Time 20% to 80% 315 715 ps odc Output Duty Cycle 48 52 % NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO /2. NOTE 2 Please refer to the Phase Noise Plot. NOTE 3 This parameter is defi ned in accordance with JEDEC Standard 65.

FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER 8421002I-01 DATA SHEET

6 REVISION B 8/14/15

TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) OFFSET FREQUENCY (HZ) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Ethernet Jitter Filter Phase Noise Result by adding Ethernet Filter to raw data Raw Phase Noise Data dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 62.5MHZ @ 3.3V 62.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.49ps OFFSET FREQUENCY (HZ) -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 100 1k 10k 100k 1M 10M 100M Ethernet Jitter Filter Phase Noise Result by adding Ethernet Filter to raw data Raw Phase Noise Data dBc Hz NOISE POWER

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PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW HSTL 2.5V/1.8V OUTPUT LOAD AC TEST CIRCUITHSTL 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT OUTPUT RISE/FALL TIME RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER 8421002I-01 DATA SHEET

8 REVISION B 8/14/15

The 8421002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below Figure 2. CRYSTAL INPUt INTERFACE and were chosen to minimize the ppm error.

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 8421002I-01 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD , V DDA , and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10µF and a .01 μF bypass capacitor should be connected to each V DDA POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING protection, a 1kΩ resistor can be tied from the REF_CLK to ground. resistance is not required but can be added for additional protection. should either be left fl oating or terminated.

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This section provides information on power dissipation and junction temperature for the 8421002I-01. Equations and example calculations are also provided. The total power dissipation for the 8421002I-01 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core) MAX = V DD_MAX * I DD_MAX = 3.465V * 122mA = 422.7mW
• Power (outputs) MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 32.8mW = 65.6mW Total Power _MAX (3.465V, with all outputs switching) = 422.7mW + 65.6mW = 488.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION

10 REVISION B 8/14/15

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 3. To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 3. HSTL DRIVER CIRCUIT AND TERMINATION

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TABLE 7. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

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TABLE 8. PACKAGE DIMENSIONS

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TABLE 9. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free Confi guration and are RoHS compliant.

FEMTOCLOCKS™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER 8421002I-01 DATA SHEET

14 REVISION B 8/14/15

Rev Table Page Description of Change Date B 3A, 3B 3 Power Supply Tables - corrected V DDO min/max. 8/8/06 Updated data sheet format. 4/6/15 B Product Discontinuation Notice - Last time buy expires August 14, 2016 PDN CQ-15-04 8/14/15

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