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Technical content

Features

  • One differential HSTL output pair
  • Crystal oscillator interface, 18pF parallel resonant crystal (24.5MHz – 34MHz)
  • Output frequency range: 245MHz – 340MHz
  • VCO range: 490MHz – 680MHz
  • RMS phase jitter at: 250MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.36ps (typical)
  • Full 3.3V or 2.5V output supply modes
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) packaging Frequency Table Inputs Output Frequency (MHz)Crystal Frequency (MHz) M N Mu ltiplication Value M/N 25 20 2 10 250 VDDA GND XTAL_OUT XTAL_IN VDD Q nQ OE OSC Phase Detector VCO 490MHz - 680MHz M = ÷20 (fixed) N = ÷2 (fixed) Q nQ OE XTAL_IN XTAL_OUT Pullup Pin Assignment 842023

8 Lead TSSOP

4.40mm x 3.0mm x 0.925 package body G Package Top View Block Diagram

842023 DATA SHEET

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1V DDA Power Analog supply pin. 2 GND Power Power supply ground. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Q/nQ outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 6, 7 nQ, Q Output Differential outp ut pair. HSTL interface levels. 8V DD Power Core supply pin.

Rev A 8/14/15 3 FEMTOCLOCK™ CRYST AL-TO-HSTL CLOCK GENERATOR Table 3B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C Table 3D. HSTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to GND. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 3E. HSTL DC Characteristics, VDD = 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to GND. NOTE 2: Defined with respect to output voltage swing at a given condition. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.11 2.5 V DD V IDD Power Supply Current 80 mA IDDA Analog Supply Current 11 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current OE V DD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 1.0 1.8 V VOL Output Low Voltage; NOTE 1 00 . 6 V VOX Output Crossover Voltage; NOTE 2 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.8 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 0.9 1.4 V VOL Output Low Voltage; NOTE 1 0.4 V VOX Output Crossover Voltage; NOTE 2 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.4 V

Table 4. Crystal Characteristics NOTE: It is not recommended to overdrive the crystal input with an external clock. NOTE 1: Please refer to Phase Noise Plots. NOTE 1: Please refer to Phase Noise Plots.

Rev A 8/14/15 5 FEMTOCLOCK™ CRYST AL-TO-HSTL CLOCK GENERATOR Typical Phase Noise at 250MHz (3.3V) 250MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.36ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR 6 Rev A 8/14/15 Typical Phase Noise at 250MHz (2.5V) 250MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical) Noise Power dBc Hz Offset Frequency (Hz)

Rev A 8/14/15 7 FEMTOCLOCK™ CRYST AL-TO-HSTL CLOCK GENERATOR Parameter Measurement Information 3.3V HSTL Output Load AC Test Circuit RMS Phase Jitter Output Rise/Fall Time 2.5V HSTL Output Load AC Test Circuit Output Duty Cycle/Pulse Width/Period SCOPE HSTL Qx nQx GND VDD VDDA 3.3V±5% 3.3V±5% 20% 80% 80% 20% tR tF VSWINGVOX nQ Q SCOPE HSTL Qx nQx GND VDD VDDA 2.5V±5% 2.5V±5% nQ Q

FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR 8 Rev A 8/14/15

Application Information

The 842023 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. Figure 1. Crystal Input Interface capacitor be connected to the VDDA pin. Figure 3. Power Supply Filtering

Figure 4. HSTL Output Termination Figure 5 shows an example of the 842023 application schematic. Note: Thermal pad (E-pad) must be connected to ground (GND). Figure 5. 842023 Schematic Example

This section provides information on power dissipation and junction temperature for the 842023. Equations and example calculations are also provided. The total power dissipation for the 842023 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core) MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (84mA + 11mA) = 329.18mW
  • Power (outputs) MAX = 94.32mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 329.18mW + 94.32mW = 423.49mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 6. Figure 6. HSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 8. JA vs. Air Flow Table for a 8 Lead TSSOP

Rev A 8/14/15 13 FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

FEMTOCLOCK™ CRYSTAL-TO-HSTL CL OCK GENERATOR 14 Rev A 8/14/15 Rev Table Page Description of Change Date A Deleted HiPerClockS references throughout. Crystal Characteristics Table - added note. Deleted application note, LVCMOS to XTAL Interface. Added Note: Thermal pad (E-pad) must be connected to ground (GND). Deleted quantity from tape and reel. 11/2/12 A Product Discontinuation Notice - Last time buy expires August 14, 2016. PDN CQ-15-04 8/14/15

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