841S104EGILFT

841S104EGILF IDT | Alldatasheet

Document overview

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Technical content

Features

• Four 0.7V current mode differential HCSL output pairs
• Crystal oscillator interface: 25MHz
• Output frequency: 100MHz
• RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.145ps (typical)
• Cycle-to-cycle jitter: 20ps (maximum)
• I2C support with readback capabilities up to 400kHz
• Spread Spectrum for electromagnetic interference (EMI) reduction
• 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
• PCI Express Gen 1, 2, 3 jitter compliant HiPerClockS™ OSC PLL Divider Network I2C Logic SDATA SCLK IREF Pullup Pullup SRCT[1:4] SRCC[1:4] 25MHz XTAL_IN XTAL_OUT ICS841S104I 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View VSS VDD VDD VSS SRCC1 SRCT1 SRCC2 SRCT2 VSS SRCC3 SRCT3 IREF SRCC4 SRCT4 SDATA SCLK nc XTAL_OUT XTAL_IN VDD VDD VDDA VSS VSS Pin AssignmentBlock Diagram

ICS841S104EGI REVISION A JUNE 18, 2010 2 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 SRCT3, SRCC3 Output Differential output pair. HCSL interface levels. 3, 9, 11, 13, 16 V SS Power Power supply ground. 4, 10, 17, 22 V DD Power Positive supply pins. 5, 6 SRCT2, SRCC2 Output Differential output pair. HCSL interface levels. 7, 8 SRCT1, SRCC1 Output Differential output pair. HCSL interface levels.

12 IREF Input

14 V DDA Power Analog supply for PLL. XTAL_OUT Input Crystal oscillator interface. XTAL_I N is the input. XTAL_OUT is the output. 20 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels. 21 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. Open drain. LVCMOS/LVTTL interface levels. 23, 24 SRCT4, SRCC4 Output Differential output pair. HCSL interface levels.

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 3 ©2010 Integrated Device Technology, Inc. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default settings upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation 6:5 Chip select address, se t to “00” to access device. 4:0 Byte offset for byte read or byte write operation. For bl ock read or block write operations, these bits must be “00000”

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 4 ©2010 Integrated Device Technology, Inc. Table 3B. Block Read and Block Write Protocol Table 3C. Byte Read and Byte Write Protocol Bit Description = Block Writ e Bit Description = Block Read 1S t a r t 1S t a r t 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9W r i t e 9W r i t e

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Byte Count - 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address - 7 bits

29:36 Data byte 1 - 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits

46 Acknowledge from slave 38 Acknowledge

Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits Data Byte N - 8 bits 47 Acknowledge Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits Stop 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge Bit Description = Byte Write Bit Description = Byte Read

1 Start 1 Start

2:8 Slave address - 7 bits 2:8 Slave address - 7 bits

9 Write 9 Write

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 20:27 Data Byte- 8 bits 20 Repeat start

29 Stop 28 Read

29 Acknowledge from slave

30:37 Data from slave - 8 bits

38 Not Acknowledge

39 Stop

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 5 ©2010 Integrated Device Technology, Inc. Control Registers Table 3D. Byte 0: Control Register 0 NOTE: Pup denotes Power-up. Table 3E. Byte 1: Control Register 1 Table 3F. Byte 2: Control Register 2 Table 3G. Byte 3:Control Register 3 Table 3H. Byte 4: Control Register 4 Table 3I. Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z) 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z) 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 20S R C SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On 1 1 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 6 ©2010 Integrated Device Technology, Inc. Table 3J. Byte 6: Control Register 6 NOTE: Pup denotes Power-up. Table 3K. Byte 7: Control Register 7 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N 6 0 TEST_MODE TEST Clock Mode Entry Control 0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 77.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.21 3.3 V DD V IDD Power Supply Current 80 mA IDDA Analog Supply Current 21 mA

ICS841S104EGI REVISION A JUNE 18, 2010 7 ©2010 Integrated Device Technology, Inc. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. is 86ps peak-to-peak for a sample size of 106 clock periods. (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 8 ©2010 Integrated Device Technology, Inc. Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz quartz crystal. NOTE 1: Refer to phase jitter plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: Measurement taken from differential waveform. NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC. NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 100 MHz fREF Reference frequency 25 MHz tjit(Ø) Phase Jitter, RMS (Random); NOTE 1 25MHz crystal, ƒ = 100MHz, Integration Range: 12kHz – 20MHz 1.145 ps tsk(o) Output Skew; NOTE 2, 3 40 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 PLL Mode 20 ps tL PLL Lock Time 50 ms FM SSC Modulation Frequency; NOTE 4 25MHz Crystal 30 32 33.33 kHz SSCRED Spectral Reduction; NOTE 4 -7 -10 dB VRB Ring-back Voltage Margin; NOTE 5, 6 -100 100 mV V MAX Absolute Max. Output Voltage; NOTE 7, 8 1150 mV VMIN Absolute Min. Output Voltage; NOTE 7, 9 -300 mV VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 250 550 mV CROSS Total Variation of VCROSS over all edges; NOTE 7, 10, 12 140 mV Rise/Fall Edge Rate; NOTE 7, 13 Measured between 150mV to +150mV 0.6 4.0 V/ns odc Output Duty Cycle 48 52 %

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 9 ©2010 Integrated Device Technology, Inc. Typical Phase Noise at 100MHz Noise Power dBc Hz Offset Frequency (Hz)

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 10 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Cycle-to-Cycle Jitter Single-ended Measurement Points for Absolute Cross Point and Swing 3.3V HCSL Output Load AC Test Circuit Output Skew Single-ended Measurement Points for Delta Cross Point 475Ω Measurement Point33Ω 50Ω 50Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF IREF VDDA VDD 3.3V±5% 3.3V±5% SRCT[1:4] ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

SRCC[1:4] VCROSS_MAX = 550mV VCROSS_MIN = 250mV VMAX = 1.15V VMIN = -0.30V SRCC SRCT 475Ω 50Ω 50Ω HCSL GND SCOPE IREF This load condition is used for IDD, tjit(cc), tjit(Ø), and tsk(o) measurements. 3.3V±5% VDDA 3.3V±5% VDD SRCCx SRCCx SRCTy SRCTy tsk(o) VCROSS_DELTA = 140mV SRCC SRCT

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 11 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information, continued Differential Measurement Points for Ringback Differential Measurement Points for Rise/Fall Edge Rate Differential Measurement Points for Duty Cycle/Period RMS Phase Jitter TSTABLE VRB -150mV VRB = -100mV VRB = +100mV +150mV 0.0V VRB TSTABLE SRCT - SRCC -150mV +150mV 0.0V Fall Edge RateRise Edge Rate SRCC - SRCT 0.0V Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) SRCT - SRCC Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers Noise Power

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 12 ©2010 Integrated Device Technology, Inc.

Application Information

Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841S104I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering pair should either be left floating or terminated.

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 15 ©2010 Integrated Device Technology, Inc. PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. Ht s() H3 s() H1 s() H2 s()–[]×= Ys() Xs() H3 s()× H1 s() H2 s()–[]×=

ICS841S104EGI REVISION A JUNE 18, 2010 16 ©2010 Integrated Device Technology, Inc. Figure 5 shows an example of ICS841S104I application schematic. close as possible to the power pin. Figure 5. ICS841S104I Application Schematic.

24 SRCT3

475 Ohm

ICS841S104EGI REVISION A JUNE 18, 2010 18 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS841S104I. Equations and example calculations are also provided. The total power dissipation for the ICS841S104I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 77.5°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection

ICS841S104EGI REVISION A JUNE 18, 2010 19 ©2010 Integrated Device Technology, Inc.

1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. Figure 7. HCSL Driver Circuit and Termination use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX.

ICS841S104EGI REVISION A JUNE 18, 2010 20 ©2010 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER ICS841S104EGI REVISION A JUNE 18, 2010 21 ©2010 Integrated Device Technology, Inc.

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS841S104I Data Sheet CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS TM CLOCK SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is su bject to change without notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without re presentation or warranty of any kind, whether ex press or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implie d warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

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