841S102

841S102 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: epieczon
• PDF pages: 26

Technical content

Features

• Two 0.7V current mode differential HCSL output pairs
• Crystal oscillator interface: 25MHz
• Output frequency: 100MHz
• RMS phase jitter @ 100MHz (12kHz – 20MHz): 1.23ps (typical)
• Cycle-to-cycle jitter: 20ps (maximum)
• I2C support with readback capabilities up to 400kHz
• Spread Spectrum for electromagnetic interference (EMI) reduction
• 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) package
• PCI Express Gen 1, 2 and 3 jitter compliant HiPerClockS™ Block Diagram Pin Assignment OSC PLL Divider Network I2C Logic SDATA SCLK IREF Pullup Pullup SRCT[1:2] SRCC[1:2] 25MHz XTAL_IN XTAL_OUT VSS VDD VSS SRCC1 SRCT1 SRCC2 SRCT2 VDD VSS IREF VDD SDATA SCLK nc XTAL_OUT XTAL_IN VDD VSS VDDA VSS 841S102 20-Lead TSSOP 4.4mm x 6.5mm x 0.925mm package body G Package Top View Crystal-to-HCSL, 100MHz PCI Express ™ Clock Synthesizer 841S102 Datasheet

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 13 VSS Power Power supply ground. 14, 20 VDD Power Power supply pins. 3, 4 SRCT2, SRCC2 Output Dif ferential output pair. HCSL interface levels. 5, 6 SRCT1, SRCC1 Output Dif ferential output pair. HCSL interface levels.

10 IREF Input

DDA Power Analog supply for PLL. 15, 16 XTAL_IN, XTAL_OUT Input Crystal oscillator interfac e. XTAL_IN is the input. XTAL_OUT is the output. 18 SCLK Input Pullup I2C compatible SCLK. This pin has an internal pullup resistor. Open drain. LVCMOS/LVTTL interface levels. 19 SDATA I/O Pullup I2C compatible SDATA. This pin has an internal pullup resistor. LVCMOS/LVTTL interface levels.

3©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal I2C serial interface is provided. Through the Serial Data Interface, various device functions, such as clock output buffers, can be individually enabled or disabled. The registers associated with the serial interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation. 6:5 Chip select address, set to “00” to access device. 4:0 Byte offset for byte read or byte wr ite operation. For block read or block write operations, these bits must be “00000”.

4©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Table 3B. Block Read and Block Write Protocol Table 3C. Byte Read and Byte Write Protocol Bit Description = Block Write Bit Description = Block Read 1S t a r t 1S t a r t 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9W r i t e 9W r i t e

10 Acknowledge from slave 10 Acknowledge from slave

11:18 Command Code - 8 bits 11:18 Command Code - 8 bits

19 Acknowledge from slave 19 Acknowledge from slave

20:27 Byte Count - 8 bits 20 Repeat start

28 Acknowledge from slave 21:27 Slave address - 7 bits

29:36 Data byte 1 - 8 bits 28 Read = 1

37 Acknowledge from slave 29 Acknowledge from slave

38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits

46 Acknowledge from slave 38 Acknowledge

Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits Data Byte N - 8 bits 47 Acknowledge Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits Stop 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge Bit Description = Byte Write Bit Description = Byte Read 1S t a r t 1S t a r t 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9W r i t e 9W r i t e 11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 20:27 Data Byte - 8 bits 20 Repeat start

29 Stop 28 Read

29 Acknowledge from slave

30:37 Data from slave - 8 bits

38 Not Acknowledge

39 Stop

5©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Control Registers Table 3D. Byte 0: Control Register 0 NOTE: Pup denotes Power-up. Table 3E. Byte 1: Control Register 1 Table 3F. Byte 2: Control Register 2 Table 3G. Byte 3:Control Register 3 Table 3H. Byte 4: Control Register 4 Table 3I. Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 1 Reserved Reserved 5 1 Reserved Reserved 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z) 1 = Enable 2 1 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved

20 S R C

0 = Spread Off, 1 = Spread On 1 1 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved

6©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Table 3J. Byte 6: Control Register 6 NOTE: Pup denotes Power-up. Table 3K. Byte 7: Control Register 7 Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N

60 T E S T _ M O D E

0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

8©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Table 6A. PCI Express Jitter Specifications, VDD = 3.3V±5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. Parameter Symbol Test Conditions Minimum Typical Maximum PCIe Industry Specification Units tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 1, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.3 19.3 86 ps tREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input High Band: 1.5MHz - Nyquist (clock frequency/2) 1.07 1.53 3.1 ps tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 2, 4 ƒ = 100MHz, 25MHz Crystal Input Low Band: 10kHz - 1.5MHz 0.19 0.32 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS; NOTE 3, 4 ƒ = 100MHz, 25MHz Crystal Input Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.18 0.3 0.8 ps

9©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized using a 25MHz quartz crystal. NOTE 1: Refer to phase jitter plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: Measurement taken from differential waveform. NOTE 6: T STABLE is the time the differential clock must maintain a minimum ± 150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measurement taken from single-ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of SRCT equals the falling edge of SRCC. NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. NOTE 12: Defined as the total variation of all crossing voltages of rising SRCT and falling SRCC, This is the maximum allowed variance in Vcross for any particular system. NOTE 13: Measured from -150mV to +150mV on the differential waveform (SRCT minus SRCC). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. Symbol Parameter Test Conditi ons Minimum Typical Maximum Units fMAX Output Frequency 100 MHz fREF Reference frequency 25 MHz tjit(Ø) Phase Jitter, RMS (Random); NOTE 1 25MHz crystal, ƒ = 100MHz, Integration Range: 12kHz – 20MHz 1.23 ps tsk(o) Output Skew; NOTE 2, 3 35 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 PLL Mode 20 ps tL PLL Lock Time 55 ms FM SSC Modulation Frequency; NOTE 4 25MHz Crystal 30 32 33.33 kHz SSCRED Spectral Reduction; NOTE 4 -7 -10 dB VRB Ring-back Voltage Margin; NOTE 5, 6 -100 100 mV VMAX Absolute Max. Output Voltage; NOTE 7, 8 1150 mV VMIN Absolute Min. Output Voltage; NOTE 7, 9 -300 mV VCROSS Absolute Crossing Voltage; NOTE 7, 10, 11 250 550 mV VCROS S Total Variation of VCROSS over all edges; NOTE 7, 10, 12 140 mV Rise/Fall Edge Rate; NOTE 7, 13 Measured between 150mV to +150mV 0.6 4.0 V/ns odc Output Duty Cycle 48 52 %

10©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Typical Phase Noise at 100MHz Noise Power dBc Hz Offset Frequency (Hz)

11©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Parameter Measurement Information 3.3V HCSL Output Load Test Circuit Cycle-to-Cycle Jitter Single-ended Measurement Points for Absolute Cross Point and Swing 3.3V HCSL Output Load Test Circuit RMS Phase Jitter Single-ended Measurement Points for Delta Cross Point Measurement Point Measurement Point GND 2pF 2pF IREF VDDA VDD 3.3V±5% 3.3V±5% SRCT1, tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

SRCC1, SRCC2 VCROSS_MAX VCROSS_MIN VMAX VMIN SRCC SRCT This load condition is used for IDD, tjit(cc), tjit(Ø), and tsk(o) measurements. 3.3V±5% VDDA 3.3V±5% VDD VCROSS SRCC SRCT

12©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Parameter Measurement Information, continued Differential Measurement Points for Ringback Differential Measurement Points for Duty Cycle/Period Differential Measurement Points for Rise/Fall Edge Rate TSTABLE VRB -150mV VRB = -100mV VRB = +100mV +150mV 0.0V VRB TSTABLE SRCT - SRCC 0.0V Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) SRCT - SRCC -150mV +150mV 0.0V Fall Edge RateRise Edge Rate SRCC - SRCT

16©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.

17©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Schematic Layout Figure 5 shows an example of the 841S102 application schematic where the device is operated at VDD = 3.3V with an 18pF parallel resonant 25MHz crystal. The schematic focuses on functional connections and is intended as an example only and may not represent the exact user configuration. For example the I 2C bus connections are shown as optionally provided via a two pin header whereas they could just as easily be driven from an FPGA. Two types of HCSL termination are shown in this schematic; one for PCIe add-in cards and one for point to point connections, which are connections on the same PCB as the 841S102. Tuning caps C1 and C2 are required for frequency accuracy. C1 = C2 = 18pF are used in this example as typical values, but their value may be adjusted slightly up or down to optimize the oscillator frequency accuracy. When routing the load caps be sure to keep all routing on the top layer. Route the ground connection of C1 and C2 together and then to a ground at the 841S102. Do not share the tuning capacitor ground with any other ground, that is ensure that only crystal current circulates in the tuning capacitors. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the V DD pin from power supply is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor on the V DD pin must be placed on the device side with direct return to the ground plane though vias. The remaining filter components can be on the opposite side of the PCB. Power supply filter component recommendations are a general guideline to be used for reducing external noise from coupling into the devices.The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.

Figure 5. 841S102 Application Schematic.

475 Ohm

This section provides information on power dissipation and junction temperature for the 841S102. Equations and example calculations are also provided. The total power dissipation for the 841S102 is the sum of the core power plus the analog, plus the power dissipated due to loading. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.

• Power (core) MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V *(75mA + 20mA) = 329.175mW
• Power (outputs) MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 44.5mW = 89mW Total Power_MAX = 329.175mW + 89mW = 418.175mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 81.3°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.418W * 81.3°C/W = 119°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection

1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. Figure 7. HCSL Driver Circuit and Termination use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX.

Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP

23©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet

Ordering Information

Table 10. Ordering Information

24©2016 Integrated Device Technology, Inc. Revision B, July 7, 2016 841S102 Datasheet Revision History Sheet Rev Table Page Description of Change Date A 16, 17 Updated the “Overdriving the XTAL Interface” note. Updated the termination note. Updated schematic and text. Spread Spectrum note, second paragraph: The 841S102 triangle modulation frequency deviation is Either 0.35% Or 0.5% down-spread from the nominal clock frequency 2/8/13 B Updated datasheet header/footer. Deleted “ICS” prefix and “I” suffix in the part number. 7/7/16

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