ICS841S012DI RENESAS | Alldatasheet

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  • Manufacturer or author: rdvorak
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Crystal-to-0.7V Differential HCSL/ LVCMOS Frequency Synthesizer 841S012DI Datasheet ©2016 Integrated Device Technology, Inc January 4, 20161 GENERAL DESCRIPTION The 841S012DI is an optimized PCIe, sRIO and Gigabit Ethernet Frequency Synthesizer and a member of high performance clock solutions from IDT. The 841S012DI uses a 25MHz parallel resonant crystal to generate 33.33MHz - 200MHz clock signals, replacing multiple oscillators and fanout buffer solutions. The device supports ±0.25% center-spread, and -0.5% down-spread clocking with two spread select pins (SSC[1:0]). The VCO operates at a frequency of 2GHz. The device has three output banks: Bank A with two 100MHz – 250MHz HCSL outputs; Bank B with seven 33.33MHz – 200MHz LVCMOS/ LVTTL outputs; and Bank C with one 33.33MHz – 200MHz LVCMOS/LVTTL output. All Banks A, B and C have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The low jitter characteristic of the 841S012DI makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet applications. Designed for networking and industrial applications, the 841S012DI can also drive the high-speed clock inputs of com- munication processors, DSPs, switches and bridges.

FEATURES

 Two 0.7V differential HCSL outputs (Bank A), confi gurable for PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz) clock signals Eight LVCMOS/LVTTL outputs (Banks B/C), 18Ω typical output impedance Two REF_OUT LVCMOS/LVTTL clock outputs, 23Ω typical output impedance  Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or one LVCMOS/LVTTL single-ended refer- ence clock input  Supports the following output frequencies: HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz, 100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz  VCO: 2GHz  Spread spectrum clock: ±0.25% center-spread (typical) and -0.6% down-spread (typical)  PLL bypass and output enable  RMS period jitter: 10ps (typical), QAx/nQAx outputs  Full 3.3V supply mode  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) package PIN ASSIGNMENT 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VDD_REFOUT REF_OUT0 REF_OUT1 GND GND REF_IN VDD VDD REF_SEL XTAL_IN XTAL_OUT BYPASS REF_OE nMR VDDOC QC GND QBC_OE VDDA VDDA VDD GND GND IREF QA0 nQA0 QA1 nQA1 GND GND SSC1 SSC0 F_SELB2 F_SELB1 F_SELB0 F_SELC2 F_SELC1 F_SELC0 F_SELA1 F_SELA0 QA_OE VDD QB6 GND QB5 VDDOB QB4 GND QB3 VDDOB VDDOB QB2 GND QB1 QB0 VDDOB 484950515253545556 47 46 45 44 43 ICS841S012DI 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View

©2016 Integrated Device Technology, Inc January 4, 20162 BLOCK DIAGRAM PLL VCO 2GHz M = ÷80 ÷NA ÷NC OSC QA0 nQA0 QA1 nQA1 QB0 QC QB1 QB2 QB3 QB4 QB5 QB6 REF_OUT0 REF_OUT1 QA_OE F_SELA[1:0] BYPASS REF_IN IREF REF_OE REF_SEL nMR SSC[1:0] XTAL_IN XTAL_OUT 25MHz Pulldown Pullup 3F_SELC[2:0] Pulldown Pullup QBC_OE Pullup F_SELB[2:0] Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Spread Spectrum ÷NB

TABLE 1. PIN DESCRIPTIONS Power Output supply pin for REF_OUT. REF_OUT1 Output Single-ended LVCMOS/LVTTL reference clock outputs. 23Ω typical output impedance. GND Power Power supply ground. 6 REF_IN Input Pulldown Single-ended LVCMOS/LVTTL reference clock input. selects crystal. LVCMOS/LVTTL interface levels. See Table 3E. OUT Input Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input. External tuning capacitor must be used for proper operation. 11 BYPASS Input Pulldown When HIGH bypasses PLL. When LOW, selects PLL. LVCMOS/LVTTL interface levels. See Table 3J. 12 REF_OE Input Pulldown Active HIGH REF_OUT enables/disables pin. LVCMOS/LVTTL interface levels. See Table 3H. dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3I. SSC0 Input Pullup SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D. Input Pulldown Frequency select pins for QBx outputs. See Table 3B. LVCMOS/LVTTL interface levels. Input Pulldown Frequency select pins for QC output. See Table 3C. LVCMOS/LVTTL interface levels. SELA0 Input Pulldown Frequency select pins for QAx/nQAx outputs. See Table 3A. LVCMOS/LVTTL interface levels. nQA0, QA0 Output Differential Bank A clock outputs. HCSL interface levels.

34 IREF Output External fi xed precision resistor (475Ω) from this pin to ground provides a

reference current used for differential current-mode QAx/nQAx clock outputs. 39 QBC_OE Input Pullup Output enable pin for Bank B and Bank C outputs. LVCMOS/LVTTL Interface levels. See Table 3G. 41 QC Output Single-ended Bank C clock output. LVCMOS/LVTTL interface levels. 18Ω typical output impedance. Power Output supply pin for QC LVCMOS output. Power Output supply pins for QBx LVCMOS outputs. Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 18Ω typical output impedance. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

©2016 Integrated Device Technology, Inc January 4, 20165 TABLE 3D. SSC FUNCTION TABLE Input ModeSSC1 SSC0 0 0 0 to -0.5% Down-spread 0 1 ±0.25% Center-spread 1 0 ±0.25% Center-spread 1 1 SSC Off (default) TABLE 3E. REF_SEL FUNCTION TABLE Input REF_SEL Input Reference 0X T A L

1 REF_IN

TABLE 3G. QBC_OE FUNCTION TABLE Input QBC_OE Function

0 QB[0:6] and QC disabled (High-Impedance)

1 (default) QB[0:6] and QC enabled TABLE 3F. QA_OE FUNCTION TABLE Input QA_OE Function

0 QA[0:1]/nQA[0:1] disabled (High-Impedance)

1(default) QA[0:1]/nQA[0:1] enabled TABLE 3H. REF_OE FUNCTION TABLE Input REF_OE Function 0 (default) REF_OUT[0:1] disabled (High-Impedance

1 REF_OUT[0:1] enabled

TABLE 3I. nMR FUNCTION TABLE Input nMR Function

0 Device reset, output divider disabled

(High-Impedance) 1 (default) Output enabled NOTE: This device requires a reset signal after power-up to function properly. TABLE 3J. BYPASS FUNCTION TABLE Input BYPASS Function 0 (default) PLL

1 Bypass (reference ÷N)

tended periods may affect product reliability. TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal.

TABLE 6. AC CHARACTERISTICS, V specifi cations after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 2: Defi ned as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 4: Measurement taken from single-ended waveform. nQx. See Parameter Measurement Information Section. fers to all crossing points for this measurement. See Parameter Measurement Information Section. for any particular system. See Parameter Measurement Information Section.

©2016 Integrated Device Technology, Inc January 4, 20168 PARAMETER MEASUREMENT INFORMATION HCSL OUTPUT SKEW 3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT LVCMOS OUTPUT SKEW RMS PERIOD JITTER LVCMOS BANK SKEW

©2016 Integrated Device Technology, Inc January 4, 20169 LVCMOS RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL CYCLE-TO-CYCLE JITTER DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD PARAMETER MEASUREMENT INFORMATION, CONTINUED SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME

©2016 Integrated Device Technology, Inc January 4, 201610

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter per- formance, power supply isolation is required. The 841S012DI provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD , V DDA , V DDOB , and V DDOC should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10 Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING protection, a 1kΩ resistor can be tied from the REF_IN to ground. resistance is not required but can be added for additional protection. pair should either be left fl oating or terminated.

FIGURE 5. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) and the inner edges of pad pattern for the leads to avoid any shorts. achieved when an array of vias is incorporated in the land pattern. Enhance Leadframe Base Package, Amkor Technology.

Figure 7 shows an example of the 841S012DI application schematic. one example of LVCMOS termination are shown in this schematic. FIGURE 7. 841S012DI SCHEMATIC EXAMPLE

475 Ohm

28 GND

27 QA_OE

26 F_SELA0

©2016 Integrated Device Technology, Inc January 4, 201616 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 841S012DI. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 841S012DI is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and HCSL Output Power Dissipation The maximum I DD current at 85° is 284mA. The HCSL output current (17mA per output pair) is included in this value. For power considerations, this output current is treated separately from the core currents, so for power calculations, I DD = 284mA - 2 * 17mA = 250mA.

  • Power (core) = V DD_MAX * (I DD + I DDA ) = 3.465V * (250mA + 20mA) = 935.6mW Power (HCSL) = 44.5mW/Load Output Pair If all outputs are loaded, the total power is 2 * 44.5mW = 89mW LVCMOS Output Power Dissipation
  • Dynamic Power Dissipation at 200MHz, (QB, QC) Power (200MHz) = C PD * Frequency * (V DDO = 19pF * 200MHz * (3.465V) = 45mW per output Total Power (200MHz) = 45mW * 8 = 360mW
  • Dynamic Power Dissipation at 25MHz, (REF_OUT) Power (25MHz) = C PD * Frequency * (V DDO = 19pF * 25MHz * (3.465V) = 5.6mW per output Total Power (25MHz) = 5.6mW * 2 = 11.2mW Total Power Dissipation
  • Total Power = Power (core) + Power (HCSL) + Total Power (200MHz) + Total Power (25MHz) = 935.6mW + 89mW + 360mW + 11mW = 1396mW

TABLE 7. THERMAL RESISTANCE θJA FOR 56 LEAD VFQFN, FORCED CONVECTION meter per second air fl ow and a multi-layer board, the appropriate value is 27.5°C/W per Table 7. and the type of board (multi-layer).

  1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. dissipation, use the following equations which assume a 50Ω load to ground. FIGURE 8. HCSL DRIVER CIRCUIT AND TERMINATION

TABLE 8. θ

TABLE 9. PACKAGE DIMENSIONS package dimensions are in Table 9 below.

TABLE 10. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc January 4, 201622 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 Removed ICS chip and Hiperclocks from the General Description. Removed ICS from the part number. Updated data sheet header and footer. 1/4/16

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