841S012BKILF | DigiCamel IC Datasheet

Online Datasheet

Read 841S012BKILF online.

ICS841S012I IDT | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 23

Technical content

Crystal-to-0.7V Differential HCSL/ LVCMOS Frequency Synthesizer ICS841S012I DATA SHEET NRND ICS841S012BKI REVISION A NOVEMBER 10, 2009 1 ©2009 Integrated Device Technology, Inc. GENERAL DESCRIPTION The ICS841S012I is an optimized PCIe, sRIO and Gigabit Ethernet Frequency Synthesizer and a member of HiperClocks™ family of high perfor- mance clock solutions from IDT. The ICS841S012I uses a 25MHz parallel resonant crystal to gener- ate 33.33MHz - 200MHz clock signals, replacing multiple oscillator and fanout buffer solutions. The device supports ±0.25% center-spread, and -0.5% down- spread clocking with two spread select pins (SSC[1:0]). The VCO operates at a fre- quency of 2GHz. The device has three output banks: Bank A with two HCSL outputs, 100MHz – 250MHz; Bank B with seven 33.33MHz – 200MHz LVCMOS/ LVTTL outputs; and Bank C with one 33.33MHz – 200MHz LVCMOS/LVTTL output. All Banks A, B and C have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The low jitter characteristic of the ICS841S012I makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet applications. Designed for networking and industrial applications, the ICS841S012I can also drive the high- speed clock inputs of communication processors, DSPs, switches and bridges. HiPerClockS™ ICS

FEATURES

Two 0.7V differential HCSL outputs (Bank A), configurable for PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz) clock signals Eight LVCMOS/LVTTL outputs (Banks B/C), 18Ω typical output impedance Two REF_OUT LVCMOS/LVTTL clock outputs, 23Ω typical output impedance Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or one LVCMOS/LVTTL single-ended reference clock input Supports the following output frequencies: HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz, 100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz VCO: 2GHz Spread spectrum clock: ±0.25% center-spread (typical) and -0.6% down-spread (typical) PLL bypass and output enable RMS period jitter: 20ps (typical), QB outputs Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Not Recommended for New Designs PIN ASSIGNMENT 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VDD REF_OUT0 REF_OUT1 GND GND REF_IN VDD VDD REF_SEL XTAL_IN XTAL_OUT BYPASS REF_OE nMR VDDOC QC GND QBC_OE VDDA VDDA VDD GND GND IREF QA0 nQA0 QA1 nQA1 GND GND SSC1 SSC0 F_SELB2 F_SELB1 F_SELB0 F_SELC2 F_SELC1 F_SELC0 F_SELA1 F_SELA0 QA_OE VDD QB6 GND QB5 VDDOB QB4 GND QB3 VDDOB VDDOB QB2 GND QB1 QB0 VDDOB 484950515253545556 47 46 45 44 43 ICS841S012I 56-Lead VFQFN 8mm x 8mm x 0.925mm package body K Package Top View

ICS841S012BKI REVISION A NOVEMBER 10, 2009 2 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER BLOCK DIAGRAM PLL VCO 2GHz M = ÷80 ÷NA ÷NC OSC QA0 nQA0 QA1 nQA1 QB0 QC QB1 QB2 QB3 QB4 QB5 QB6 REF_OUT0 REF_OUT1 QA_OE F_SELA[1:0] BYPASS REF_IN IREF REF_OE REF_SEL nMR SSC[1:0] XTAL_IN XTAL_OUT 25MHz Pulldown Pullup 3F_SELC[2:0] Pulldown Pullup QBC_OE Pullup F_SELB[2:0] Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Spread Spectrum ÷NB

ICS841S012BKI REVISION A NOVEMBER 10, 2009 5 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TABLE 3D. SSC FUNCTION TABLE tupnI edoM1CSS0 CSS 00 d aerps-nwoD%5.0-ot0 01 d aerps-retneC%52.0± 10 d aerps-retneC%52.0± 11 ) tluafed(ffOCSS TABLE 3E. REF_SEL FUNCTION TABLE tupnI LES_FER ecnerefeRtupnI )tluafed(0L ATX 1N I_FER TABLE 3G. QBC_OE FUNCTION TABLE tupnI EO_CBQ noitcnuF 0) ecnadepmI-hgiH(delbasidCQdna]6:0[BQ )tluafed(1d elbaneCQdna]6:0[BQ TABLE 3F. QA_OE FUNCTION TABLE tupnI EO_AQ noitcnuF 0) ecnadepmI-hgiH(delbasid]1:0[AQn/]1:0[AQ )tluafed(1d elbane]1:0[AQn/]1:0[AQ TABLE 3H. REF_OE FUNCTION TABLE tupnI EO_FER noitcnuF )tluafed(0) ecnadepmI-hgiH(delbasid]1:0[TUO_FER 1d elbane]1:0[TUO_FER TABLE 3I. nMR FUNCTION TABLE tupnI RMn noitcnuF 0 delbasidredividtuptuo,tesereciveD )ecnadepmI-hgiH( )tluafed(1d elbanetuptuO otpu-rewopretfalangisteseraseriuqerecivedsihT:ETON .ylreporpnoitcnuf TABLE 3J. BYPASS FUNCTION TABLE tupnI SSAPYB noitcnuF )tluafed(0L LP 1) N÷ecnerefer(ssapyB

ICS841S012BKI REVISION A NOVEMBER 10, 2009 8 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION RREF = 475Ω Measurement Point0Ω 50Ω 50Ω0Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF HCSL OUTPUT SKEW 3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS GND 1.65V±5% -1.65V±5% VDDA 1.65V±5% VDD VDDA t sk(o) VDDOX VDDOX t sk(o) Qx nQx Qy nQy Qx Qy LVCMOS OUTPUT SKEW VDD, VDDOB, VDDOC 3.3V±5% 3.3V±5% RMS PERIOD JITTER LVCMOS BANK SKEW t sk(b) VDDOX VDDOX Qx:Qx Qx:Qx (where X = Bank B or Bank C) VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram

ICS841S012BKI REVISION A NOVEMBER 10, 2009 9 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION, CONTINUED LVCMOS RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tPERIOD tPW tPERIOD odc = VDDOX x 100% tPW QC, QB0:QB6 DIFFERENTIAL CYCLE-TO-CYCLE JITTER ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1

1000 Cycles

DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD Q - nQ 0.0V Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT Q nQ VCROSS_DELTA SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING nQ Q VCROSS_MAX VCROSS_MIN VMAX VMIN 20% 80% 80% 20% tR tF QC, QB0:QB6 DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate nQA[0:1] QA[0:1]

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS841S012I pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA, VDDOB, and V DDOC should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10 Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. The 10 Ω resistor can also be replaced by a ferrite bead. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING tied from XTAL_IN to ground. protection, a 1kΩ resistor can be tied from the REF_IN to ground. protection. A 1k Ω resistor can be used. that there is no trace attached. pair should either be left floating or terminated.

ICS841S012BKI REVISION A NOVEMBER 10, 2009 15 ©2009 Integrated Device Technology, Inc. = 3.3V. The 18pF parallel resonant 25MHz crystal is used. close as possible to the power pin. FIGURE 7. ICS841S012I SCHEMATIC EXAMPLE power-up to function properly.

28 GND

27 QA_OE

26 F_SELA0

475 Ohm

ICS841S012BKI REVISION A NOVEMBER 10, 2009 16 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS841S012I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS841S012I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. Core and HCSL Output Power Dissipation The maximum IDD current at 85° is 300mA. The HCSL output current (17mA per output pair) is included in this value. For power considerations, this output current is treated separately from the core current, so for power calculations, I DD = 300mA - 2 * 17mA = 266mA.

Power (core) = VDD_MAX * (IDD + IDDA ) = 3.465V * (266mA + 20mA) = 991.0mW Power (HCSL) = 44.5mW/Load Output Pair If all outputs are loaded, the total power is 2 * 44.5mW = 89mW LVCMOS Output Power Dissipation
Dynamic Power Dissipation at 200MHz (QB, QC) Power (200MHz) = CPD * Frequency * (VDDO)2 = 4pF * 200MHz * (3.465V) 2 = 9.6mW per output Total Power (200MHz) = 9.6mW * 8 = 76.7mW
Dynamic Power Dissipation at 25MHz (REF_OUT) Power (25MHz) = C PD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V) 2 = 1.2mW per output Total Power (25MHz) = 1.2mW * 2 = 2.4mW Total Power Dissipation
Total Power = Power (core) + Power (HCSL) + Total Power (200MHz) + Total Power (25MHz) = 991.0mW + 89mW + 76.7mW + 2.4mW = 1159mW

ICS841S012BKI REVISION A NOVEMBER 10, 2009 17 ©2009 Integrated Device Technology, Inc. TABLE 7. THERMAL RESISTANCE θθθθθJA FOR 56 LEAD VFQFN, FORCED CONVECTION of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. Assuming 1 meter per second air flow and a multi-layer board, the appropriate value is 31.4°C/W per Table 7. flow, and the type of board (multi-layer).

Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. dissipation, use the following equations which assume a 50 Ω load to ground. The highest power dissipation occurs at maximum V DD . FIGURE 8. HCSL DRIVER CIRCUIT AND TERMINATION

ICS841S012BKI REVISION A NOVEMBER 10, 2009 20 ©2009 Integrated Device Technology, Inc. TABLE 9. PACKAGE DIMENSIONS this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9 below.

ICS841S012BKI REVISION A NOVEMBER 10, 2009 21 ©2009 Integrated Device Technology, Inc. TABLE 10. ORDERING INFORMATION reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

ICS841S012BKI REVISION A NOVEMBER 10, 2009 22 ©2009 Integrated Device Technology, Inc. ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER TEEHSYROTSIHNOISIVER veRe lbaTe gaPe gnahCfonoitpircseDe taD A A4T6 IotsnoitidnoCtseTdedda-elbaTscitsiretcarahCCDylppuSrewoP DD .wor .Fp22/Fp51otFp33morfecafretnItupnIlatsyrC,2erugiFdetadpU .tuoyaLcitamehcSdetadpU 90/11/8 A 1. tellubdnaDNRNddA 90/01/9

800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support netcom@idt.com +480-763-2056

6024 Silver Creek Valley Road

San Jose, CA 95138 ICS841S012I Data Sheet CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved. www.IDT.com

Product Information

841S012BKILF specifications and overview.

Summary

Crystal-to-0.7V Differential HCSL/LVCMOS Frequency Synthesizer

Description

Crystal-to-0.7V Differential HCSL/LVCMOS Frequency Synthesizer

Source title 841S012BKILF Datasheet(PDF) - Integrated Device Technology

Related Parts

More parts from the same family.

Browse manufacturer