841S01 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 18
Technical content
Features
- One 0.7V current mode differential HCSL output pair
- Crystal oscillator interface: 25MHz
- Output frequency: 100MHz
- RMS period jitter: 3ps (maximum)
- Cycle-to-cycle jitter: 35ps (maximum)
- I2C support with readback capabilities up to 400kHz
- Spread Spectrum for electromagnetic interference (EMI) reduction
- 3.3V operating supply mode
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package Divider NetworkPLLOSC I2C Logic SRCT0 SRCC0 Pullup Pullup XTAL_IN XTAL_OUT SDATA SCLK IREF 25MHz VDD SDATA SCLK XTAL_OUT XTAL_IN VDD VSS VDDAVSS IREF VSS VDD SRCC0 SRCT0 VDD VSS 841S01 16-Lead TSSOP 5mm x 4.4mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram
Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 6, 8, 10 V SS Power Ground for core and SRC outputs. 2, 5, 11, 16 V DD Power Power supply for core and SRC outputs. 3, 4 SRCT0, SRCC0 Output Differential output pair. HCSL interface levels.
7 IREF Input
9V DDA Power Analog supply pin. XTAL_OUT Input Crystal oscillator interface. XTAL _IN is the input. XTAL_OUT is the output. high-impedance in power-down mode. LVCMOS/LVTTL interface levels. in high-impedance in power-down mode. LVCMOS/LVTTL interface levels.
Rev B 11/16/15 3 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore, use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3A. The block write and block read protocol is outlined in Table 3B, while Table 3C outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3A.Command Code Definition Table 3B. Block Read and Block Write Protocol Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation. 6:5 Chip select address, se t to “00” to access device. 4:0 Byte offset for byte read or byte write operation. For bl ock read or block write operations, these bits must be “00000”. Bit Description = Block Writ e Bit Description = Block Read 1S t a r t 1S t a r t 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9W r i t e 9W r i t e
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code - 8 bits 11:18 Command Code - 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte Count - 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address - 7 bits
29:36 Data byte 1 - 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 2 - 8 bits 30:37 Byte Count from slave - 8 bits
46 Acknowledge from slave 38 Acknowledge
Data Byte/Slave Acknowledges 39:46 Data Byte 1 from slave - 8 bits Data Byte N - 8 bits 47 Acknowledge Acknowledge from slave 48:55 Data Byte 2 from slave - 8 bits Stop 56 Acknowledge Data Bytes from Slave/Acknowledge Data Byte N from slave - 8 bits Not Acknowledge
Rev B 11/16/15 4 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Table 3C. Byte Read and Byte Write Protocol Control Registers Table 4A. Byte 0: Control Register 0 NOTE: Pup denotes Power-up. Table 4B. Byte 1: Control Register 1 Table 4C. Byte 2: Control Register 2 Table 4D. Byte 3:Control Register 3 NOTE: Pup denotes Power-up. Bit Description = Byte Write Bit Description = Byte Read
1 Start 1 Start
2:8 Slave address - 7 bits 2:8 Slave address - 7 bits
9 Write 9 Write
11:18 Command Code - 8 bits 11:18 Command Code - 8 bits 20:27 Data Byte- 8 bits 20 Repeat start
29 Stop 28 Read
29 Acknowledge from slave
30:37 Data from slave - 8 bits
38 Not Acknowledge
39 Stop
Bit @Pup Name Description 7 0 Reserved Reserved 6 1 Reserved Reserved 5 1 Reserved Reserved 4 1 Reserved Reserved 3 1 Reserved Reserved 2 1 SRC[T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z) 1 = Enable 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 20S R C SRC Spread Spectrum Enable 0 = Spread Off, 1 = Spread On 1 1 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 1 Reserved Reserved 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved
Rev B 11/16/15 5 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Table 4E. Byte 4: Control Register 4 Table 4F. Byte 5: Control Register 5 Table 4G. Byte 6: Control Register 6 Table 4H. Byte 7: Control Register 7 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Bit @Pup Name Description 7 0 TEST_SEL REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N
60 T E S T _ M O D E
0 = Normal Operation, 1 = REF/N or Hi-Z Mode 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Bit @Pup Name Description 3 0 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 1 Vendor ID Bit 0
Rev B 11/16/15 6 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 86.9C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.22 3.3 V DD V IDD Power Supply Current 80 mA IDDA Analog Supply Current 22 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2.2 V VIL Input Low Voltage 1.0 V IIH Input High Current SDATA, SCLK V DD = VIN = 3.465V 10 µA IIL Input Low Current SDATA, SCLK V DD = 3.465V, VIN = 0V -150 µA
Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. NOTE 1: With recommended crystal. NOTE 2: Measured at crossing point VOX. NOTE 3: Measured using a 50 to GND termination. NOTE 4: Measured at crossing point VOX at 100MHz. multiplier. For example, for a bit error rate of 10E-12, the peak-to-peak jitter would be 2.42ps x 14 = 33.88ps. NOTE 6: Measured from VOL = 0.175V to VOH = 0.525V. NOTE 7: Determined as a fraction of 2*(tR – tF) / (tR + tF). NOTE 8: The device will operate reliably with input duty cycles up to 30/70% but the REF clock duty cycle will not be within specification.
Rev B 11/16/15 8 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Cycle-to-Cycle Jitter HCSL Output Rise/Fall Time RMS Period Jitter Output Duty Cycle/Pulse Width/Period 3.3V±5% 3.3V±5% VDD VDDA SRCT0 tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
(First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram SRCT0 SRCC0
Table 7. Recommended Crystal Specifications mirror and output drive details. Figure 1. HCSL Current Mirror and Output Drive
This section provides information on power dissipation and junction temperature for the 841S01. Equations and example calculations are also provided. The total power dissipation for the 841S01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 86.9°C/W per Table 8 below. Table 8. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. Figure 4. HCSL Driver Circuit and Termination use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX.
Table 9. JA vs. Air Flow Table for a 16 Lead TSSOP
PCI EXPRESSTM CLOCK GENERATOR 15 Rev B 11/16/15 841S01 DATA SHEET
Ordering Information
Table 11. Ordering Information NOTE: Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev B 11/16/15 16 PCI EXPRESSTM CLOCK GENERATOR 841S01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B T4A 4 Corrected Control Register Table. 8/31/12 Updated data sheet format. 11/16/15
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