841N4830

841N4830_16 IDT | Alldatasheet

Document overview

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Technical content

Features

• Fourth generation FemtoClock® Next Generation (NG) technology
• Three differential HCSL outputs, one differential LVPECL and two single-ended LVCMOS/LVTTL outputs
• Crystal oscillator interface designed for a 25MHz, 12pF parallel resonant crystal
• CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, HCSL
• A 25MHz crystal generates output frequencies of: 100MHz, 50MHz and 25MHz
• VCO frequency: 2GHz
• RMS Phase Jitter @ 100MHz, (12kHz – 20MHz) using a 25MHz crystal: 0.36ps (maximum)
• Power supply noise rejection PSNR: -45dB (typical)
• PCI Express Gen 2 (5 Gb/s) jitter compliant
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 PLL_BYPASS nOE_REF nOEB DIV2_QB VDDA CLK nCLK VDDO_REF QA1 nQA1 VDDO QA2 nQA2 GND QA3 V DDO_QA3 REF_OUT nREF_OUT CLK_SEL XTAL_IN XTAL_OUT VDD_OSC VDDO_QB QB VDD nOEA VDDO IREF QA0 nQA0 GND V DDA 841N4830 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ÷80 ÷20 OSC PFD LPF QA[2:0] nQA[2:0] QA3 QB XTAL_IN XTAL_OUT nOE_REF CLK_SEL IREF DIV2_QB nOEB 25MHz LVPECL 100MHz HCSL 100MHz LVCMOS 100/50MHz LVCMOS 25MHz PLL_BYPASS nOEA REF_OUT nREF_OUT CLK nCLK Pulldown Pulldown Pulldown Pulldown Pulldown Pullup Pullup Pullup FemtoClock® NG VCO 2GHz 841N4830 Datasheet FemtoClock ® NG Crystal-to-HCSL Frequency Synthesizer

Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. LOW outputs are driven by PLL. LVCMOS/LVTTL interface levels. See Table 3D. 2 nOE_REF Input Pulldown Output enable signal for REF_OUT output. When LOW, outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3C. selects high impedance mode. LVCMOS/LVTTL interface levels.See Table 3B. 5, 32 V DDA Power Analog supply pins. 6 CLK Input Pulldown Non-inverting differential clock input. 7 nCLK Input Pullup Inverting differential clock input. 8V DDO_REF Power Output power supply pin for LVPECL reference outputs. nREF_OUT Output 25MHz differential reference output pair. LVPECL interface levels. inputs. LVCMOS/LVTTL interface levels.See Table 3E. XTAL_OUT Input Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. 14 V DD_OSC Power Core supply pin for crystal oscillator. 15 V DDO_QB Power Output power supply pin for Bank B LVCMOS output. 16 QB Output Single-ended output. LVCMOS/LVTTL interface levels. 17 V DDO_QA3 Power Output power supply pin for QA3 LVCMOS output. 18 QA3 Output Single-ended output. LVCMOS/LVTTL interface levels. 19, 25 GND Power Power supply ground. 20, 21 nQA2, QA2 Output 100MHz differential output pair. HCSL interface levels. 22, 29 V DDO Power Output power supply pins for Bank A HCSL outputs. 23, 24 nQA1, QA1 Output 100MHz differential output pair. HCSL interface levels. 26, 27 nQA0, QA0 Output 100MHz differential output pair. HCSL interface levels.

28 IREF

high impedance mode. LVCMOS/LVTTL interface levels.See Table 3A. 31 V DD Power Core supply pin.

Table 2. Pin Characteristics

1 High-Impedance

1 Bypass PLL

4©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDD_OSC = 3.0V to 3.6V, VDDO = VDDO_QA3 = VDDO_QB = VDDO_REF = 2.7V to 3.6V, TA = -40°C to 85°C VDDOx denotes VDDO_REF, VDDO_QA3 and VDDO_QB. Item Rating Supply Voltage, VDD 3.63V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO (LVCMOS, HCSL) Outputs, IO (LVPECL) Continuos Current Surge Current -0.5V to VDDO + 0.5V 50mA 100mA Package Thermal Impedance, JA 37.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD, VDD_OSC Core Supply Voltage 3.0 3.3 3.6 V VDDA Analog Supply Voltage VDD – 0.32 3.3 V DD V VDDO, VDDOx Output Supply Voltage 2.7 3.3 3.6 V IEE Power Supply Current 170 mA IDDA Analog Supply Current Included in I EE 32 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_SEL, DIV2_QB VDD = VIN = 3.6V 5 µA nOEA, nOEB, nOE_REF, PLL_BYPASS VDD = VIN = 3.6V 150 µA IIL Input Low Current CLK_SEL, DIV2_QB VDD = 3.6V, VIN = 0V -150 µA nOEA, nOEB, nOE_REF, PLL_BYPASS VDD = 3.6V, VIN = 0V -5 µA

NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 1: Output termination with 50 to VDDO_REF – 2V. Table 5. Crystal Characteristics

6©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Using a 25MHz, 12pF quartz crystal. NOTE 1: Refer to the Phase Noise plot. NOTE 2: Outputs are terminated with 50 to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency QB PLL mode 50 MHz QA3 PLL mode 100 MHz PLL Bypass 20 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 100MHz, Integration Range: 12kHz – 20MHz 0.34 ps tR / tF Output Rise/Fall Time 200 600 ps odc Output Duty Cycle 47 53 % VOH Output High Voltage; NOTE 2 QA3, QB 2.2 V VOL Output Low Voltage; NOTE 2 QA3, QB ƒ  100MHz 0.9 V Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency REF_OUT, nREF_OUT 25 MHz tR / tF Output Rise/Fall Time REF_OUT, nREF_OUT 20% to 80% 100 600 ps odc Output Duty Cycle REF_OUT, nREF_OUT 49 51 %

7©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function. NOTE 3: Measurement taken from single ended waveform. NOTE 4: Measurement taken from differential waveform. NOTE 5: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. NOTE 6: Measured at the crosspoint where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ. NOTE 7: Refers to the total variation from the lowest crosspoint to the highest, regardless of which edge is crossing. Refers to all crosspoints for this measurement. NOTE 8: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in VCROSS for any particular system. NOTE 9: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 10: This parameter is defined in accordance with JEDEC Standard 65. NOTE 11: See Phase Noise Plot. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency PLL 100 MHz PLL Bypass 20 MHz fREF Reference Frequency 25 MHz tsk(b) Bank Skew; NOTE 1, 10 50 ps tjit(Ø) Phase Jitter, RMS (Random); NOTE 11 100MHz, Integration Range: 12kHz – 20MHz 0.36 ps tREFCLK_HF_RMS Phase Jitter RMS; NOTE 2 100MHz, 25MHz crystal input High Band: 1.5MHz - Nyquist (clock frequency/2) 0.600 ps tREFCLK_LF_RMS Phase Jitter RMS; NOTE 2 100MHz, 25MHz crystal input Low Band: 10kHz - 1.5MHz 0.023 ps tjit(cc) Cycle-to-Cycle Jitter PLL Mode 30 ps tL PLL Lock Time 10 ms VRB Ring-back Voltage Margin; NOTE 4, 9 -100 100 mV tSTABLE Time before VRB is allowed; NOTE 4, 9 500 ps VHIGH Voltage High 520 920 mV VLOW Voltage Low -150 150 mV VCROSS Absolute Crossing Voltage; NOTE 3, 6, 7 160 460 mV VCROSS Total Variation of VCROSS over all edges; NOTE 3, 6, 8 140 mV Rising Edge Rate; NOTE 4, 5 0.6 4.0 V/ns Falling Edge Rate; NOTE 4, 5 0.6 4.0 V/ns PSNR Power Supply Noise Reduction -45 dB odc Output Duty Cycle; NOTE 4 49 51 %

8©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Typical Phase Noise at 100MHz (3.3V) Noise Power dBc Offset Frequency (Hz)

9©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Parameter Measurement Information 3.3V LVPECL Output Load Test Circuit 3.3V HCSL Output Load Test Circuit Differential Input Level 3.3V LVCMOS Output Load Test Circuit 3.3V HCSL Output Load Test Circuit Output Rise/Fall Time (LVPECL, LVCMOS) SCOPE REF_OUT nREF_OUT VEE VDD, -1.3V±0.3V VDDA VDDO_REF VDD_OSC 1.85V±0.15V VDDA 33Ω 50Ω 50Ω33Ω 49.9Ω 49.9Ω 2pF 2pF Qx nQxVEE 475Ω475Ω 3.15V±14.3% VDDA VDDO VDD_OSC VDD, VDDA This load condition is used for VHIGH, VLOW, VRB, tSTABLE and VCROSS, VCROSS measurements. 3.3V±9.1% 3.3V±9.1% nCLK CLK VDD GND V CMR Cross Points VPP SCOPE Q VEE 1.65V±9.1% -1.65V±9.1% VDDO_QA3, VDDAVDD, 1.65V±9.1% VDDOB, VDD_OSC, VDDA 1.575V±0.225V 50Ω 50Ω SCOPE Qx nQxVEE 475Ω475Ω VDDA VDDO VDD_OSC VDD, VDDA This load condition is used for IDD, tjit(cc), tsk(b), odc and tjit(Ø) measurements. 3.3V±9.1% 20% 80% 80% 20% tR tF VSWING nREF_OUT QA3, QB, REF_OUT

10©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Parameter Measurement Information, continued RMS Phase Jitter LVCMOS Output Duty Cycle/Pulse Width/Period PLL Lock Time LVPECL Output Duty Cycle/Pulse Width/Period Cycle-to-Cycle Jitter Bank Skew tPERIOD tPW tPERIOD odc = x 100% tPW QA3, QB nREF_OUT REF_OUT nQA[0:2] tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA[0:2] nQAx QAx nQAx QAx tsk(b)

11©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Parameter Measurement Information, continued Differential Measurement Points for Duty Cycle/Period Differential Measurement Points for Rise/Fall Edge Rate Differential Measurement Points for Ringback Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing TSTABLE TSTABLE VRB VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V

15©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Recommendations for Unused Input Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Output The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Differential Outputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom- mended only as guidelines. The differential outputs are low impedance follower outputs that gen- erate ECL/LVPECL compatible outputs. Therefore, terminating resis- tors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 6A and 6B show two different layouts which are recommended only as guide- lines. Other suitable clock layouts may exist and it would be recom- mended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 6A. 3.3V LVPECL Output Termination Figure 6B. 3. 3V LVPECL Output Termination 84 84 3.3VR3 125 125 Zo = 50 Zo = 50 Input 3.3V 3.3V

17©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Schematic Example Figure 8 shows an example of 841N4830 application schematic. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In this example, the device is operated at VDD = VDDO_REF = VDD_OSC = VDDO = 3.3V. The 12pF parallel resonant 25MHz crystal is used. The C1 = 5pF and C2 = 5pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. When designing the circuit board, return the capacitors to ground though a single point contact close to the package. Two examples of HCSL terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 841N4830 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.

Figure 8. 841N4830 Application Schematic

25 M H zC1

19©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.

20©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 841N4830. Equations and example calculations are also provided. 1. Power Dissipation The total power dissipation for the 841N4830 is the sum of the core power plus the power dissipated due to loading. The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3A and 3B for details on calculating power dissipation due to loading. Core  Power(core) = V DD_MAX * IEE = 3.6V * 170mA = 612mW LVPECL Output LVPECL driver power dissipation is 30mW/Loaded output pair, total LVPECL output dissipation:  Power(LVPECL) = 30mW HSCL Output HSCL driver power dissipation is 46.8mW/Loaded output pair, total HSCL output dissipation:  Power(HSCL) = 46.75mW * 3 = 140.25mW LVCMOS Output  Output Impedance R OUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 25)] = 24mA  Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 25 * (24mA)2 = 14.4mW per output  Total Power Dissipation on the ROUT Total Power (ROUT) = 14.4mW * 2 = 28.8mW Dynamic Power Dissipation at 100MHz Power (100MHz) = CPD * Frequency * (VDD)2 = 5pF * 100MHz * (3.6V)2 = 6.48mW per output Total Power (100MHz) = 6.48mW * 2 = 12.96mW Total Power Dissipation  Total Power = Power (core) + Power(LVPECL) + Power(HCSL) + Total Power (ROUT) + Total Power (100MHz) = 612mW + 30mW + 140.25mW + 28.8mW +12.96mW = 824mW

that the bond wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 37.7°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection

3A. Calculations and Equations for LVPECL. The purpose of this section is to calculate power dissipation on the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 9. Figure 9. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.

Table 8. JA vs. Air Flow Table for a 32 Lead VFQFN

Table 9. Package Dimensions package dimensions are in Table 9.

1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)

26©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet

Ordering Information

Table 10. Ordering Information Table 11. Pin 1 Orientation in Tape and Reel Packaging

27©2016 Integrated Device Technology, Inc. Revision F, May 23, 2016 841N4830 Datasheet Revision History Sheet Rev Table Page Description of Change Date B T6A T6C General Description: Maximum rms phase jitter changed to 0.34ps Per PCN: Features: changed to: RMS Phase Jitter @ 100MHz, (12kHz – 20MHz) using a 25MHz crystal: 0.34ps (maximum) Added 0.34 Maximum to tjit RMS Phase Jitter. Added 0.34 Maximum to tjit, RMS Phase Jitter., Added 0.582 Typical to tREFCLK_HF_RMS RMS Phase Jitter. Added 0.023 Typical to tREFCLK_LF_RMS RMS Phase Jitter. Added updated Phase Noise Plot. Added updated PCI Express Application Note Changed Package Drawing Changed Marking to ICSN4830BIL. 3/5/12 C T4A 4 Per PCN #N1206-01, changed I EE to 170mA Max. Changed device reference to ICS841N4830BKI throughout the datasheet. 8/29/12 D T4A T6A T6C 4 - 7 19 - 20, 22 Per PCN #N1206-01 General Description and Features, updated RMS Phase Jitter spec to 0.36ps. DC / AC Characteristic Tables - changed voltage supply table descriptions. Power Supply DC Characteristics Table - changed Core supply voltage min / max specs; changed VDDO supply voltage min / max specs; corrected VDDA min spec from VDD - 0.16V to VDD - 0.32V. LVCMOS AC Characteristic Table - changed odc min / max spec. HCSL AC Characteristic Table - changed Phase Jitter, RMS (Random) max spec.; changed Phase Jitter (HF_RMS) typical spec.; changed Cycle-to-Cycle max spec. Parameter Measurement Information - updated Test Circuit diagrams. PCI Express Application Note - deleted Gen 1 information. Power Considerations - changed VDD = 3.465V to VDD = 3.6V, updated equations. 1/22/2013 D 17, 18 Updated schematic 8/5/2013 E T11 T10 Added P1 Orientation in Tape and Reel Table. Ordering Information - Added W part number. 7/1/15 F Updated datasheet header/footer. 5/23/16

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