841N254B RENESAS | Alldatasheet
Document overview
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Technical content
Datasheet sections
Features
▪ Fourth generation FemtoClock ® (NG) technology ▪ Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output clock synthesized from a 25MHz fundamental mode crystal ▪ Four differential clock outputs (two LVDS and two HCSL outputs) ▪ Crystal interface designed for 25MHz, parallel resonant crystal ▪ RMS phase jitter at 156.25MHz, using a 25MHz crystal (1MHz - 20MHz): 0.27ps (typical) ▪ RMS phase jitter at 156.25MHz, using a 25MHz crystal (12kHz - 20MHz): 0.32ps (typical) ▪ Power supply noise rejection PSNR: -50dB (typical) ▪ LVCMOS interface levels for the frequency select input ▪ Full 3.3V or 2.5V supply voltage ▪ Lead-free (RoHS 6) packaging ▪ -40°C to 85°C ambient operating temperature Block Diagram Inputs Output Frequency with fXTAL = 25MHzF_SEL1 F_SEL0 0 (default) 0 (default) 156.25MHz 0 1 125MHz 1 0 100MHz 1 1 250MHz NOTE: F_SEL[1:0] are asynchronous controls. 841N254B Datasheet FemtoClock® NG Crystal-to-LVDS/ HCSL Clock Synthesizer
3©2013–2023 Renesas Electronics Corporation February 2, 2023 841N254B Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions [a] Pulldown refers to internal input resistors. See Table 2 for typical values.
Description
1, 8, 13, 32 VDD Power Core supply pins. 2, 4 nc Unused No connect. 3 VDDA Power Analog power supply. 5, 17, 23, 25, 31 GND Power Power supply ground. 6 REF_CLK Input Pulldown Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels. 7 nOEA Input Pulldown Output enable input. See Table 6 for function. LVCMOS/LVTTL interface levels. 9 nOEB Input Pulldown Output enable input. See Table 7 for function. LVCMOS/LVTTL interface levels. 10 REF_SEL Input Pulldown Reference select input. See Table 4 for function. LVCMOS/LVTTL interface levels. 11, XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 14 BYPASS Input Pulldown Bypass mode select pin. See Table 5 for function. LVCMOS/LVTTL interface levels. 15, F_SEL0, F_SEL1 Input Pulldown Frequency select pin. See Table 3 for function. LVCMOS/LVTTL interface levels. 18, 19 QA1, nQA1 Output Differential clock output. LVDS interface levels. 20 VDDOA Power Output supply pin for QAx outputs. 21, 22 QA0, nQA0 Output Differential clock output. LVDS interface levels.
24 IREF Input External fixed precision resistor (475 ) from this pin to ground provides a
reference current used for differential current-mode QBx, nQBx clock outputs. 26, 27 nQB1, QB1 Output Differential clock output. HCSL interface levels. 28 VDDOB Power Output supply pin for QBx outputs. 29, 30 nQB0, QB0 Output Differential clock output. HCSL interface levels. Table 2. Pin Characteristics
Table 3. Output Divider and Output Frequency [a] F_SEL[1:0] are asynchronous controls. Table 4. PLL Reference Clock Select Function Table [a] REF_SEL is an asynchronous control.
1 The REF_CLK input is selected as reference clock
Table 5. PLL BYPASS Function Table [a] BYPASS is an asynchronous control. feedback divider of 25 and then divided by the selected output divider N. output divider N. AC specifications do not apply in PLL bypass mode. Table 6. nOEA Output Enable Function Table [a] nOEA is an asynchronous control.
1 QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 7. nOEB Output Enable Function Table [a] nOEB is an asynchronous control.
1 QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
Table 8. Absolute Maximum Ratings
Table 9. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Table 10. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = Table 11. LVDS 3.3V DC Characteristics, VDD = VDDOA = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Table 12. Crystal Characteristics Table 13. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
been reached under these conditions. NOTE: Characterized using a 25MHz crystal. NOTE 1: Please refer to the phase noise plots. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 5: Measurement taken from differential waveform. to drop back into the V RB ±100mV differential range. NOTE 7: Measurement taken from single ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ. See Parameter Measurement Information Section. for this measurement. See Parameter Measurement Information Section. any particular system. See Parameter Measurement Information Section. measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
9©2013–2023 Renesas Electronics Corporation February 2, 2023 841N254B Datasheet Typical Phase Noise at 156.25MHz (3.3V) Typical Phase Noise at 156.25MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.32ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1MHz to 20MHz = 0.27ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz)
1k resistor can be tied from the REF_CLK to ground. required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. should either be left floating or terminated. reliably drive the clock reference input of a IDT S-RIO switch. Please refer to IDT’s S-RIO device datasheet for more details. Figure 19. LVDS-to-S-RIO 2.0 Reference Clock Interface
Figure 24. Recommended Termination (Where a point-to-point connection can be used) range of the input receivers should be verified for compatibility with the output. Figure 25. Typical LVDS Driver Termination
100 Differential Transmission Line
filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. stability suggests adding bulk capacitance in the local area of all devices. tables in the datasheet to ensure that the logic control inputs are properly set. Figure 27. 841N254B Application Schematic
This section provides information on power dissipation and junction temperature for the 841N254B . Equations and example calculations are also provided. The total power dissipation for the 841N254B is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. that the bond wire and bond pad temperature remains below 125°C. and a multi-layer board, the appropriate value is 37.7°C/W per Table 14. type of board (multi-layer). Table 14. Thermal Resistance JA for 32-Lead VFQFN, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 28. Figure 28. HCSL Driver Circuit and Termination dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when V DD_MAX. Table 15. JA vs. Air Flow Table for a 32-lead VFQFN
23©2013–2023 Renesas Electronics Corporation February 2, 2023 841N254B Datasheet Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.renesas.com/us/en/document/psc/package-outline-drawing-package-code-nlg32p1-32-vfqfpn-50-x-50-x-09-mm-body-05-mm-pitch
Ordering Information
Revision History
Part Number Marking Package Carrier Type Temperature Range 841N254BKI LF ICS1N254BIL Lead-Free 32-Lead VFQFN Tray -40C to 85C 841N254BKI LFT ICS1N254BIL Lead-Free 32-Lead VFQFN Tape and Reel -40C to 85C Revision Date Description of Change February 2, 2023 Updated POD link in Package Outline Drawings section. April 17, 2018 Updated the package out drawings; however, no technical changes Completed other minor changes throughout the document May 23, 2016 Updated datasheet header/footer. Deleted “ICS” prefix from part number throughout the datasheet. November 4, 2013 Replacement part for ICS841N254AKI, per PCN# N1309-01.
5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW 25 321 891617 3.15 ±0.15 3.15 ±0.15 24 0.20 0.50 0.40 0.25 (0.525) 0.20 Package Outline 3.15 5.304.20 5.30 3.15 0.250.50 (PCB Top View, NSMD Design) SIDE VIEW RECOMMENDED LAND PATTERN© Renesas Electronics Corporation
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