841N254B_18 IDT | Alldatasheet
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1©2018 Integrated Device Technology, Inc. April 17, 2018
Description
The 841N254B is a 4-output clock synthesizer designed for S-RIO 1.3 and 2.0 reference clock applications. The device generates four copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz clock signal with excellent phase jitter performance. The four outputs are organized in two banks of two LVDS and two HCSL ouputs. The device uses IDT’s fourth generation FemtoClock ® NG technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. The synthesize d clock frequency and the phase-noise performance are optimized for driving RIO 1.3 and 2.0 SerDes reference clocks. The device supports 3.3V and 2.5V voltage supplies and is packaged in a small 32-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Function Table Fe a t ure s ▪ Fourth generation FemtoClock ® (NG) technology ▪ Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output clock synthesized from a 25MHz fundamental mode crystal ▪ Four differential clock outputs (two LVDS and two HCSL outputs) ▪ Crystal interface designed for 25MHz, parallel resonant crystal ▪ RMS phase jitter at 156.25MHz, using a 25MHz crystal (1MHz - 20MHz): 0.27ps (typical) ▪ RMS phase jitter at 156.25MHz, using a 25MHz crystal (12kHz - 20MHz): 0.32ps (typical) ▪ Power supply noise rejection PSNR: -50dB (typical) ▪ LVCMOS interface levels for the frequency select input ▪ Full 3.3V or 2.5V supply voltage ▪ Lead-free (RoHS 6) packaging ▪ -40°C to 85°C ambient operating temperature Block Diagram Inputs Output Frequency with fXTAL = 25MHzF_SEL1 F_SEL0 0 (default) 0 (default) 156.25MHz 0 1 125MHz 1 0 100MHz 1 1 250MHz NOTE: F_SEL[1:0] are asynchronous controls. 841N254B Datasheet Fe m t oClock® NG Crystal-to-LVDS/ HCSL Clock Synthesizer
3©2018 Integrated Device Technology, Inc. April 17, 2018 841N254B Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions [a] Pulldown refers to internal input resistors. See Table 2 for typical values. 1, 8, 13, 32 V DD Power Core supply pins. 2, 4 nc Unused No connect. 3V DDA Power Analog power supply. 5, 17, 23, 25, 31 GND Power Power supply ground. 6 REF_CLK Input Pulldown Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels. 7 nOEA Input Pulldown Output enable input. See Table 6 for function. LVCMOS/LVTTL interface levels. 9 nOEB Input Pulldown Output enable input. See Table 7 for function. LVCMOS/LVTTL interface levels. 10 REF_SEL Input Pulldown Reference select input. See Table 4 for function. LVCMOS/LVTTL interface levels. 11, XTAL_IN, XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 14 BYPASS Input Pulldown Bypass mode select pin. See Table 5 for function. LVCMOS/LVTTL interface levels. 15, F_SEL0, F_SEL1 Input Pulldown Frequency select pin. See Table 3 for function. LVCMOS/LVTTL interface levels. 18, 19 QA1, nQA1 Output Differential clock output. LVDS interface levels. 20 V DDOA Power Output supply pin for QAx outputs. 21, 22 QA0, nQA0 Output Differential clock output. LVDS interface levels.
24 IREF Input External fixed precision resistor (475 ) from this pin to ground provides a
reference current used for differential current-mode QBx, nQBx clock outputs. 26, 27 nQB1, QB1 Output Differential clock output. HCSL interface levels. 28 V DDOB Power Output supply pin for QBx outputs. 29, 30 nQB0, QB0 Output Differential clock output. HCSL interface levels. Table 2. Pin Characteristics
Table 3. Output Divider and Output Frequency [a] F_SEL[1:0] are asynchronous controls. Table 4. PLL Reference Clock Select Function Table [a] REF_SEL is an asynchronous control.
1 The REF_CLK input is selected as reference clock
Table 5. PLL BYPASS Function Table [a] BYPASS is an asyn chronous control. feedback divider of 25 and then divided by the selected output divider N. output divider N. AC specifications do not apply in PLL bypass mode. Table 6. nOEA Output Enable Function Table [a] nOEA is an asynchronous control.
1 QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods ma y affect product reliability. Table 7. nOEB Output Enable Function Table [a] nOEB is an asynchronous control.
1 QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
Table 8. Absolute Maximum Ratings
Table 9. Pow er Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, T A = -40°C to 85°C Table 10. LVCMOS/LVTTL Input DC Characteristics, V DD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, T A = Table 11. LVDS 3.3V DC Characteristics, VDD = VDDOA = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Table 12. Crystal Characteristics Table 13. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, T A = -40°C to 85°C
been reached under these conditions. NOTE: Characterized using a 25MHz crystal. NOTE 1: Please refer to the phase noise plots. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 5: Measurement taken from differential waveform. to drop back into the V RB ±100mV differential range. NOTE 7: Measurement taken from single ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter M easurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Meas urement Information Section. NOTE 10: Measured at crossing point where the instantaneous volt age value of the rising edge of Q equals the fa lling edge of nQ . See Parameter Measurement Information Section. for this measurement. See Parameter Measurement Information Section. any particular system. Se e Parameter Meas urement Information Section. measurement region for rise and fall time. The 300mV measuremen t window is centered on the differential zero crossing.
9©2018 Integrated Device Technology, Inc. April 17, 2018 841N254B Datasheet Typical Phase Noise at 156.25MHz (3.3V) Typical Phase Noise at 156.25MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.32ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1MHz to 20MHz = 0.27ps (typical) Noise Power (dBc/Hz) Offset Frequency (Hz)
filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approxi mately 10kHz. stability suggests adding bulk capacitance in the local area of all devices. tables in the datasheet to ensure that the logic control inputs are properly set. Figure 27. 841N254B Application Schematic
This section provides information on power dissipation and junction temperature for the 841N254B. Equations and example calculations are also provided. The total power dissipation for the 841N254B is the sum of the core power plus the analog power plus t he power dissipated in th e load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. that the bond wire and bond pad temperature remains below 125°C. type of board (multi-layer). Table 14. T hermal Resistance JA for 32-Lead VFQFN, Forced Convection
DISCLAIMER Integrated Device Te chnology, Inc. (IDT) and its aff iliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specific ations described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. The informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of IDT's products for any particular purpose, an implied warran ty of merchantability, or non-infringement of the intellectual p roperty rights of others. This documen t is presented only as a guide and does not convey any license under intellectual propert y rights of IDT or any third parties. IDT's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other c ountries. Other trademarks used herein are the property Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
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San Jose, CA 95138 USA www.IDT.com 23©2018 Integrated Device Technology, Inc. April 17, 2018 841N254B Datasheet Package Outline Draw ings The package outline drawings are appended at the end of this document and are accessible from the link be low. The package infor mation is the most current data available. www.idt.com/document/psc/n lnlg-32-package-out line-50-x-50-mm-body-epad- 315-x-315-050- mm-pitch-qfn
Ordering Information
Revision History
Orderable Part Number Marking Package Carrier Type Temperature 841N254BKILF ICS1N254BIL Lead-Free 32-Lead VFQFN Tray -40 C to 85 C 841N254BKILFT ICS1N254BIL Lead-Free 32-Lead VFQFN Tape and Reel -40 C to 85 C Revision Date Description of Change April 17, 2018 Updated the package out drawings; however, no technical changes Completed other minor changes throughout the document May 23, 2016 Updated datasheet header/footer. Deleted “ICS” prefix from part number throughout the datasheet. November 4, 2013 Replacement part for ICS841N254AKI, per PCN# N1309-01.
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,QWHJUDWHG'HYLFH7HFKQRORJ\\,QF NLG32P1, PSC-4171-01, Rev 02, Page 2 Package Revision History Rev No.Date Created Description Feb 8, 2016 Rev 01 Added "k: Value April 12, 2018 Rev 02 New Format