ICS841N254I IDT | Alldatasheet
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- Fourth generation FemtoClock® (NG) technology Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output clock synthesized from a 25MHz fundamental mode crystal Four differential clock outputs (two LVDS and two HCSL outputs) Crystal interface designed for 25MHz, parallel resonant crystal RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1MHz - 20MHz): 0.27ps (typical) RMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz - 20MHz): 0.32ps (typical) Power supply noise rejection PSNR: -50dB (typical) LVCMOS interface levels for the frequency select input Full 3.3V or 2.5V supply voltage Available in both standard (RoHS 5) and Lead-free (RoHS 6) packages -40°C to 85°C ambient operating temperature Function Table NOTE: F_SEL[1:0] are asynchronous controls. Inputs Output Frequency with fXTAL = 25MHzF_SEL1 F_SEL0 0 (default) 0 (default) 156.25MHz 0 1 125MHz 1 0 100MHz 1 1 250MHz QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 Pulldown Pulldown Pulldown Pulldown Pulldown OSC XTAL_IN XTAL_OUT REF_CLK REF_SEL BYPASS F_SEL[0:1] nOEA nOEB IREF ÷25 PFD LPF FemtoClock® NG VCO 625MHzPulldown LVDS LVDS HCSL HCSL 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VDD nc VDDA nc GND REF_CLK nOEA VDD IREF GND nQA0 QA0 VDDOA nQA1 QA1 GND nOEB REF_SEL XTAL_IN XTAL_OUT VDD BYPASS F_SEL0 F_SEL1 GND QB0 nQB0 VDDOB QB1 nQB1 GND VDD ICS841N254I 32-lead VFQFN K Package 5mm x 5mm x 0.925mm package body Top View Block Diagram Pin Assignment
ICS841N254AKI REVISION A APRIL 18, 2011 2 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 8, 13, 32 V DD Power Core supply pins. 3V DDA Power Analog power supply. 23, 25, 31 GND Power Power supply ground. 6 REF_CLK Input Pulldown Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels. 7 nOEA Input Pulldown Output enable input. See Table 3D for function. LVCMOS/LVTTL interface levels. 9 nOEB Input Pulldown Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels. 10 REF_SEL Input Pulldown Reference select input. See Table 3B for function. LVCMOS/LVTTL interface levels. XTAL_OUT Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 14 BYPASS Input Pulldown Bypass mode select pin. See Table 3C for function. LVCMOS/LVTTL interface levels. F_SEL1 Input Pulldown Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. 18, 19 QA1, nQA1 Output Differential clock output. LVDS interface levels. 20 V DDOA Power Output supply pin for QAx outputs. 21, 22 QA0, nQA0 Output Differential clock output. LVDS interface levels.
24 IREF Input External fixed precision resistor (475Ω) from this pin to ground provides a reference
current used for differential current-mode QBx, nQBx clock outputs. 26, 27 nQB1, QB1 Output Differential clock output. HCSL interface levels. 28 V DDOB Power Output supply pin for QBx outputs. 29, 30 nQB0, QB0 Output Differential clock output. HCSL interface levels.
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 3 ©2011 Integrated Device Technology, Inc. Function Tables Table 3A. Output Divider and Output Frequency NOTE: F_SEL[1:0] are asynchronous controls. Table 3B. PLL Reference Clock Select Function Table NOTE: REF_SEL is an asynchronous control. Table 3C. PLL BYPASS Function Table NOTE: BYPASS is an asynchronous control. Table 3D. nOEA Output Enable Function Table NOTE: nOEA is an asynchronous control. Table 3E. nOEB Output Enable Function Table NOTE: nOEB is an asynchronous control. Inputs Operation f OUT with fREF = 25MHzF_SEL1 F_SEL0 0 (default) 0 (default) f OUT = fREF * 25 ÷ 4 156.25MHz 01f OUT = fREF * 5 125MHz 10f OUT = fREF * 4 100MHz 11f OUT = fREF * 10 250MHz Input OperationREF_SEL 0 (default) The crystal interface is selected as reference clock
1 The REF_CLK input is selected as reference clock
0 (default) PLL is enabled. The reference frequency f REF is multiplied by the PLL feedback divider of 25 and then divided by the selected output divider N. 1 PLL is bypassed. The reference frequency fREF is divided by the selected output divider N. AC specifications do not apply in PLL bypass mode. Input OperationnOEA 0 (default) QA0, nQA0 and QA1, nQA1 outputs are enabled
1 QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
0 (default) QB0, nQB0 and QB1, nQB1 outputs are enabled
1 QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 4 ©2011 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 3.6V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO (HCSL) -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 37.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD – 0.30 3.3 V DD V VDD – 0.30 2.5 V DD V VDDOA&B Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDDA Analog Supply Current 30 mA IDD Power Supply Current 113 mA IDDOA&B Output Supply Current 72 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current nOEA, nOEB, BYPASS, REF_SEL, REF_CLK, F_SEL[1:0] VDD = VIN = 2.625V or 3.465V 150 µA IIL Input Low Current nOEA, nOEB, BYPASS, REF_SEL, REF_CLK, F_SEL[1:0] VDD = 2.625V or 3.465V, VIN = 0V -5 µA
ICS841N254AKI REVISION A APRIL 18, 2011 5 ©2011 Integrated Device Technology, Inc. Table 5. Crystal Characteristics
ICS841N254AKI REVISION A APRIL 18, 2011 6 ©2011 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = VDDOA = VDDOB = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C has been reached under these conditions. NOTES continued on next page.
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 7 ©2011 Integrated Device Technology, Inc. NOTE: Characterized using a 25MHz crystal. NOTE 1: Please refer to the phase noise plots. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 5: Measurement taken from differential waveform. NOTE 6: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measurement taken from single ended waveform. NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ. See Parameter Measurement Information Section. NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 12: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 8 ©2011 Integrated Device Technology, Inc. Typical Phase Noise at 156.25MHz (3.3V) Typical Phase Noise at 156.25MHz (3.3V) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.32ps (typical) Noise Power dBc Hz Offset Frequency (Hz) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 156.25MHz RMS Phase Jitter (Random) 1MHz to 20MHz = 0.27ps (typical) Noise Power dBc Hz Offset Frequency (Hz)
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 9 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit 2.5V HCSL Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit 3.3V HCSL Output Load AC Test Circuit 2.5V HCSL Output Load AC Test Circuit SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +– Float GND VDDA VDD, VDDOA, 475Ω 33Ω 50Ω 50Ω33Ω 49.9Ω 49.9Ω HCSL GND 2pF 2pF Qx nQx IREF 3.3V±5% 3.3V±5% VDDA VDD, VDDOB 475Ω 33Ω 50Ω 50Ω33Ω 49.9Ω 49.9Ω HCSL GND 2pF 2pF Qx nQx IREF 2.5V±5% 2.5V±5% VDDA VDD, VDDOB SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +– Float GND VDDA VDD, VDDOA, 475Ω 50Ω 50Ω HCSL GND SCOPE IREF This load condition is used for IDD, tjit(Ø), tsk(b) and tsk(o) measurements. 3.3V±5% VDDA 3.3V±5% VDD, VDDOB This load condition is used for IDD, tjit(Ø), tsk(b) and tsk(o) measurements. 475Ω 50Ω 50Ω HCSL GND SCOPE IREF 2.5V±5% VDDA 2.5V±5% VDD, VDDOB
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 10 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued RMS Phase Jitter Output Skew Differential Measurement Points for Ringback LVDS Output Duty Cycle/Pulse Width/Period Bank Skew Differential Measurement Points for Duty Cycle/Period Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power nQx Qx nQy Qy tsk(o) TSTABLE TSTABLE VRB VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V tPW tPERIOD tPW tPERIOD odc = x 100% nQA[0:1] QA[0:1] nQX0 QX1 nQX0 QX1 tsk(b) Where X = Bank A or Bank B Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) Q - nQ 0.0V
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER ICS841N254AKI REVISION A APRIL 18, 2011 11 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued HCSL Differential Measurement Points for Rise/Fall Time Single-ended Measurement Points for Delta Cross Point Offset Voltage Setup Differential Measurement Points for Rise/Fall Edge Rate Single-ended Measurement Points for Absolute Cross Point/Swing Differential Output Voltage Setup Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate Q nQ VCROSS_DELTA out out LVDSDC Input ➤ VOS/∆ VOS VDD Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate nQ Q VCROSS_MAX VCROSS_MIN VMAX VMIN 100 out out LVDSDC Input VOD/∆ VOD VDD
ICS841N254AKI REVISION A APRIL 18, 2011 15 ©2011 Integrated Device Technology, Inc. at the receiver and a 100Ω differential transmission line environment. Figure 4. Typical LVDS Driver Termination
ICS841N254AKI REVISION A APRIL 18, 2011 18 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS841N254I. Equations and example calculations are also provided. The total power dissipation for the ICS841N254I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V , which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 37.7°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
ICS841N254AKI REVISION A APRIL 18, 2011 19 ©2011 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. Figure 7. HCSL Driver Circuit and Termination use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX.
ICS841N254AKI REVISION A APRIL 18, 2011 20 ©2011 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 32-lead VFQFN
ICS841N254AKI REVISION A APRIL 18, 2011 21 ©2011 Integrated Device Technology, Inc. Table 9. Package Dimensions package dimensions are in Table 9.
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
ICS841N254AKI REVISION A APRIL 18, 2011 22 ©2011 Integrated Device Technology, Inc. Table 10. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS841N254I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without re presentation or warranty of any kind, whether e xpress or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an imp lied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.
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