ICS841664I IDT | Alldatasheet
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FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841664I IDT™ / ICS™ HCSL CLOCK GENERATOR 1 ICS841664AGI REV. A JANUARY 30, 2009 PRELIMINARY GENERAL DESCRIPTION The ICS841664I is an optimized sRIO clock generator and member of the HiPerClocks™ family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to gen- erate 125MHz and 156.25MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suit- able to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial applications, the ICS841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches and bridges.
FEATURES
Four differential HCSL clock outputs: configurable for sRIO (125MHz or 156.25MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input Supports the following output frequencies: 125MHz or 156.25MHz VCO: 625MHz PLL bypass and output enable RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz): 0.35ps (typical) @ 125MHz Full 3.3V power supply mode -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS BLOCK DIAGRAM M = ÷25 ÷NA ÷NB OSC FemtoClock PLL VCO = 625MHz XTAL_IN XTAL_OUT REF_IN REF_SEL IREF BYPASS FSEL[0:1] MR/nOE nREF_OE QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 REF_OUT Pulldown Pulldown Pulldown Pulldown Pulldown Pullup PIN ASSIGNMENT ICS841664I 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View VDD REF_OUT GND QA0 nQA0 VDDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_SEL VDDA IREF FSEL0 FSEL1 QB0 nQB0 VDDOB GND QB1 nQB1 MR/nOE VDD XTAL_IN XTAL_OUT GND The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS
IDT™ / ICS™ HCSL CLOCK GENERATOR 3 ICS841664AGI REV. A JANUARY 30, 2009 ICS841664I FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR PRELIMINARY TABLE 3B. REF_SEL FUNCTION TABLE TABLE 3D. MR/nOE FUNCTION TABLE TABLE 3C. BYPASS FUNCTION TABLE tupnI LES_FERe cnerefeRtupnI 0L ATX 1N I_FER tupnI SSAPYBn oitarugifnoCLLP 0n oLLP 1) N/ferf=BQ,AQ(dessapybLLP .)hctilgtuptuoesuacyam(noitcnuf.rhcnysA:1ETON tupnI EOn/RMn oitcnuF 1ETON 0d elbanestuptuO 1) woL(delbasidstuptuo,tesereciveD .)hctilgtuptuoesuacyam(noitcnuf.rhcnysA:1ETON TABLE 3A. FSELX FUNCTION TABLE (fref = 25MHZ) TABLE 3E. nREF_OE FUNCTION TABLE tupnI EO_FERnn oitcnuF 1ETON 0d elbaneTUO_FER 1) ecnadepmihgih(delbasidTUO_FER .)hctilgtuptuoesuacyam(noitcnuf.rhcnysA:1ETON stupnIs gnitteSycneuqerFstuptuO 1LESF0 LESFM 1 :0AQn/1:0AQ1 :0BQn/1:0BQ 00 5 2) zHM521(5/OCV) zHM521(5/OCV 015 2) zHM521(5/OCV) zHM52.651(4/OCV 10 5 2) zHM521(5/OCVH =1:0BQn,L=1:0BQ 11 5 2) zHM52.651(4/OCV) zHM52.651(4/OCV
IDT™ / ICS™ HCSL CLOCK GENERATOR 4 ICS841664AGI REV. A JANUARY 30, 2009 ICS841664I FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO_X + 0.5V Package Thermal Impedance, θJA 64.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 531.33 .35 64.3V V ADD egatloVylppuSgolanAV DD 51.0–3 .35 64.3V V ,AODD V BODD egatloVylppuStuptuO 531.33 .35 64.3V I DD tnerruCylppuSrewoP 07A m I ADD tnerruCylppuSgolanA 51A m I ,AODD I BODD tnerruCylppuStuptuO 57A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 2V DD 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tnerruChgiHtupnI ,LES_FER,NI_FER ,EOn/RM,SSAPYB 1LESF,0LESF V DD V= NI V564.3=0 51A µ EO_FERnV DD V= NI V564.3=5 A µ I LI tnerruCwoLtupnI ,LES_FER,NI_FER ,EOn/RM,SSAPYB 1LESF,0LESF V DD V,V564.3= NI V0=5 -A µ EO_FERnV DD V,V564.3= NI V0=0 51-A µ V HO ;egatloVhgiHtupuO 1ETON TUO_FERV DD V564.3=5 72.2V V LO ;egatloVwoLtupuO 1ETON TUO_FERV DD V564.3=5 77.0V Z TUO ecnadepmItuptuOT UO_FERV DD V564.3=0 2 Ω 05htiwdetanimretstuptuO:1ETON Ω Vot DD ,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/ .margaidtiucriCtseTdaoLtuptuO
TABLE 5. CRYSTAL CHARACTERISTICS
IDT™ / ICS™ HCSL CLOCK GENERATOR 6 ICS841664AGI REV. A JANUARY 30, 2009 ICS841664I FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR PRELIMINARY TYPICAL PHASE NOISE AT 156.25MHZ AT 3.3V 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.35ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 125MHZ AT 3.3V 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.35ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER sRIO Filter Raw Phase Noise Data Phase Noise Result by adding an sRIO Filter to raw data sRIO Filter Raw Phase Noise Data Phase Noise Result by adding an sRIO Filter to raw data
IDT™ / ICS™ HCSL CLOCK GENERATOR 7 ICS841664AGI REV. A JANUARY 30, 2009 ICS841664I FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION HCSL OUTPUT SKEW 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power t sk(o) Qy Qx nQy nQx LVCMOS OUTPUT RISE/FALL TIME HCSL OUTPUT RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tPW tPERIOD tPW tPERIOD odc = x 100% QA0, QA1, QB0, QB1 nQA0, nQA1, nQB0, nQB1 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW REF_OUT HCSL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD SCOPE Qx LVCMOS 1.65V±5% -1.65V±5% GND VDD VDDA 1.65V±5% Measurement Point HSCL 33Ω 50Ω 50Ω33Ω Measurement Point 50Ω 50Ω 475Ω 3.3V±5% GND VDD, VDDOA, VDDOB 3.3V±5%, VDDA 20% 80% 80% 20% tR tF QA0, QA1, QB0, QB1 nQA0, nQA1, nQB0, nQB1 0.175V 0.525V 0.525V 0.175V tR tF VSWING REF_OUT
This section provides information on power dissipation and junction temperature for the ICS841664I. Equations and example calculations are also provided. The total power dissipation for the ICS841664I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results.
- Power (core) MAX = V DD_MAX * (I DD + I DDA ) = 3.465V * (70mA + 15mA) = 294.5mW
- Power (outputs) MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 44.5mW = 178mW LVCMOS Output Power Dissipation
- Dynamic Power Dissipation at 25MHz Power (25MHz) = C PD * Frequency * (V DD)2 = 18pF * 25MHz * (3.465V) 2 = 5.40mW per output Total Power Dissipation
- Total Power = Power (core) + Power (Outputs) + Total Power (25MHz) = 294.5mW + 178mW + 5.4mW = 477.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE θθθθθJA FOR 28-LEAD TSSOP, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. dissipation, use the following equations which assume a 50 Ω load to ground. The highest power dissipation occurs when V DD_MAX. FIGURE 6. HCSL DRIVER CIRCUIT AND TERMINATION
TABLE 8. θ
TABLE 10. ORDERING INFORMATION reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.
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San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA