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841654 REVISION A 4/20/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 841654 is an optimized PCIe and sRIO clock generator. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the 841654 can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges.
FEATURES
Four differential HCSL clock outputs: confi gurable for PCIe (100MHz) and sRIO (100MHz or 125MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output Selectable crystal oscillator interface, 25MHz, 18pF parallel reso- nant crystal or LVCMOS/LVTTL single-ended reference clock input Supports the following output frequencies: 100MHz or 125MHz VCO: 500MHz PLL bypass and output enable RMS phase jitter at 100MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) Full 3.3V power supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 841654 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View VDD REF_OUT GND QA0 nQA0 VDDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_SEL VDDA IREF FSEL0 FSEL1 QB0 nQB0 V DDOB GND QB1 nQB1 MR/nOE V DD XTAL_IN XTAL_OUT GND M = ÷20 ÷NA ÷NB OSC FemtoClock PLL VCO = 500MHz XTAL_IN XTAL_OUT REF_IN REF_SEL IREF BYPASS FSEL[0:1] MR/nOE nREF_OE QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 REF_OUT Pulldown Pulldown Pulldown Pulldown Pulldown Pullup
841654 DATA SHEET
2 REVISION A 4/20/15
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 2 REF_OUT Output Single-ended reference frequency clock output. LVCMOS/LVTTL interface levels. 3, 7, 15, 22 GND Power Power supply ground. QA1, nQA1 Ouput Differential Bank A output pairs. HCSL interface levels. Power Output supply pin for Bank A outputs. 10 nREF_OE Input Pullup Active low REF_OUT enable/disable. See Table 3E. LVCMOS/LVTTL interface levels. 11 BYPASS Input Pulldown Selects PLL operation/PLL bypass operation. See Table 3C. LVCMOS/LVTTL interface levels. 12 REF_IN Input Pulldown Single-ended PLL reference clock input. LVCMOS/LVTTL interface levels. 13 REF_SEL Input Pulldown Reference select. Selects the input reference source. See Table 3B. LVCMOS/LVTTL interface levels.
19 MR/nOE Input Pulldown
enabled. See Table 3D. LVCMOS/LVTTL interface levels. nQB0, QB0 Output Differential Bank B output pairs. HCSL interface levels. Power Output supply pin for Bank B outputs. FSEL0 Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
28 IREF Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
3 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
TABLE 3B. REF_SEL FUNCTION TABLE TABLE 3D. MR/nOE FUNCTION TABLE TABLE 3C. BYPASS FUNCTION TABLE Input REF_SEL Input Reference
0 XTAL (default)
1 REF_IN
BYPASS PLL Confi guration NOTE 1
0 PLL on (default)
1 PLL bypassed (QA, QB = fref/N)
NOTE 1: Asynchronous function. Input MR/nOE Function NOTE 1
0 Outputs enabled (default)
1 Device reset, outputs disabled (High Impedance)
NOTE 1: Asynchronous function. TABLE 3A. FSELX FUNCTION TABLE (f ref = 25MHZ) TABLE 3E. nREF_OE FUNCTION TABLE Input nREF_OE Function NOTE 1
0 REF_OUT enabled
1 REF_OUT disabled (High Impedance) (default)
NOTE 1: Asynchronous function. Inputs Outputs Frequency Settings FSEL1 FSEL0 M QA0:1/nQA0:1 QB0:1/nQB0:1 0 0 20 VCO/5 (100MHz) VCO/5 (100MHz) (default) 0 1 20 VCO/5 (100MHz) VCO/4 (125MHz) 1 0 20 VCO/5 (100MHz) QB0:1 = L, nQB0:1 = H 1 1 20 VCO/4 (125MHz) VCO/4 (125MHz)
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
4 REVISION A 4/20/15
Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, V O -0.5V to V DDOX + 0.5V Package Thermal Impedance, θ JA 64.4°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY CHARACTERISTICS, V DD = V DDOA = V DDOB TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Core Supply Voltage 3.135 3.3 3.465 V V DDA Analog Supply Voltage V DD – 0.20 3.3 3.465 V V DDOA, V DDOB Output Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current Unterminated 85 mA I DDA Analog Supply Current Unterminated 20 mA I DDOA and I DDOB Output Supply Current Unterminated, RREF = 475 Ω ± 1% 5 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 2 V DD + 0.3 V V IL Input Low Voltage -0.3 0.8 V I IH Input High Current REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 V DD = V IN = 3.465 V 150 µA nREF_OE V DD = V IN = 3.465V 5 µA I IL Input Low Current REF_IN, REF_SEL, BYPASS, MR/nOE, FSEL0, FSEL1 V DD = 3.465V, V IN = 0V -5 µA nREF_OE V DD = 3.465V, V IN = 0V -150 µA V OH Ouput High Voltage; NOTE 1 REF_OUT V DD = 3.465V 2.6 V V OL Ouput Low Voltage; NOTE 1 REF_OUT V DD = 3.465V 0.5 V Z OUT Output Impedance REF_OUT V DD = 3.465V 20 Ω NOTE 1: Outputs terminated with 50Ω to V DD /2. See Parameter Measurement Information Section, Output Load Test Circuit diagram.
5 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal. NOTE: All specifi cations are taken at 100MHz and 125MHz. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
6 REVISION A 4/20/15
TYPICAL PHASE NOISE AT 125MHZ 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER TYPICAL PHASE NOISE AT 100MHZ 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical) OFFSET FREQUENCY (HZ) dBc Hz NOISE POWER Filter Raw Phase Noise Data Phase Noise Result by adding an Filter to raw data Filter Raw Phase Noise Data Phase Noise Result by adding a Filter to raw data
7 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
PARAMETER MEASUREMENT INFORMATION 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT HCSL OUTPUT LOAD AC TEST CIRCUIT 3.3V±5% HCSL OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER CYCLE-TO-CYCLE JITTER 3.3V±5% VDD, VDDOA, VDDOB 3.3V±5% 3.3V±5% VDDA VDD, VDDOA, VDDOB VDDA HCSL OUTPUT SKEW tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
nQA[0:1], nQB[0:1] QA[0:1], QB[0:1]
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
8 REVISION A 4/20/15
PARAMETER MEASUREMENT INFORMATION, CONTINUED LVCMOS OUTPUT RISE/FALL TIME 20% 80% 80% 20% tR tF LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME 0.175V 0.525V 0.525V 0.175V tR tF VSWING DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD SE MEASUREMENT POINTS FOR DELTA CROSS POINT DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK REF_OUT nQAx, nQBx QAx, QBx
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PARAMETER MEASUREMENT INFORMATION, CONTINUED SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 841654 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, V DDA, V DDOA and V DDOB should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10 Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING protection, a 1kΩ resistor can be tied from the REF_IN to ground. resistance is not required but can be added for additional protection. should either be left fl oating or terminated. that there is no trace attached.
10 REVISION A 4/20/15
FIGURE 2. CRYSTAL INPUt INTERFACE chosen to minimize the ppm error. is shown in Figure 3. The XTAL_OUT pin can be left fl oating. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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Figure 4 shows an example of 841654 application schematic. In this example, the device is operated at V CC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted F IGURE 4. 841654 SCHEMATIC LAYOUT nREF_OE TL3 Zo = 50 RU2 Not Install 475 TL5 Zo = 50 .1uf Zo = 50 R5 33 V DDOA =3.3V VDD 27pF V DDOB=3.3VMR/nOE VDD VCCOA 10u VDDOA R12 LVCMOS 25MHz RD2 R1 33 To Logic Input pins 0.1u VDD 0.1u VDDA VDD 0.1u Set Logic Input to '0' BYPASS Logic Control Input Examples R13 Using for PCI Express Add-In Card To Logic Input pins R2 33 RD1 Not Install VDD=3.3V VDD VCCOB .1uf REF_SEL 50VDDOB ICS841654I VDD REF_OUT GND QA0 nQA0 VDDA VDDOA GND QA1 nQA1 nREF_OE BYPASS GND XTAL_OUT XTAL_IN VDD MR/nOE nQB1 QB1 GND VDDOB nQB0 REF_IN REF_SEL IREF FSEL0 FSEL1 QB0 TL2 Zo = 50 27pF Set Logic Input to '1' VDD TL4 Zo = 50 FSEL0 18pF HCSL Termination FSEL1 REF_OUT VDD VDD RU1 Using for PCI Express Point-to-Point Connection for optimizing frequency accuracy. One example of HCSL and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin.
12 REVISION A 4/20/15
This section provides information on power dissipation and junction temperature for the 841654. Equations and example calculations are also provided. The total power dissipation for the 841654 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V DD_MAX * I DD_MAX = 3.465V * 85mA = 294.5mW
- Power (outputs) MAX = 50.06mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 50.06mW = 200.24mW Total Power _MAX (3.465V, with all outputs switching) = 294.5mW + 200.24mW = 494.74mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 64.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 28-LEAD TSSOP, FORCED CONVECTION
13 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 4. dissipation, use the following equations which assume a 50Ω load to ground. FIGURE 4. HCSL DRIVER CIRCUIT AND TERMINATION
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
14 REVISION A 4/20/15
Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 5A. RECOMMENDED TERMINATION Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. FIGURE 5B. RECOMMENDED TERMINATION
15 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
TABLE 8. θ
16 REVISION A 4/20/15
TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
17 FEMTOCLOCKS™ CRYSTAL-TO-HCSL
Rev Table Page Description of Change Date A T10 16 Ordering Information - removed leaded devices. Updated data sheet format. 4/20/15
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