ICS841608I IDT | Alldatasheet
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FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR ICS841608I IDT™ / ICS™ HCSL CLOCK GENERATOR 1 ICS841608AKI REV. A JUNE 18, 2008 GENERAL DESCRIPTION The ICS841608I is an optimized PCIe and sRIO clock generator and member of the HiPerClocks™ family of high-performance clock solutions from IDT. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (<1ps rms) suitable for clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the ICS841608I can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges.
FEATURES
Eight HCSL outputs: configurable for PCIe (100MHz) and sRIO (125MHz) clock signals Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input Supports the following output frequencies: 100MHz or 125MHz VCO: 500MHz PLL bypass and output enable PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant RMS phase jitter @125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.37ps (typical) Full 3.3V power supply mode -40°C to 85°C ambient operating temperature Available in both standard and (RoHs 5) lead-free (RoHS 6) packages HiPerClockS™ ICS BLOCK DIAGRAM PIN ASSIGNMENT M = ÷20 (default) OSC FemtoClock PLL VCO = 500MHz XTAL_IN XTAL_OUT REF_SEL FSEL MR/nOE IREF BYPASS REF_IN Pulldown Pulldown Pulldown Pulldown Pulldown nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_IN XT AL_OUT MR/nOE V DD nQ0 nQ1 nQ4 VDD nQ3 nQ2 GND FSEL IREF BYPASS V DDA REF_SEL REF_IN VDD GND VDD nQ7 nQ6 GND nQ5 ICS841608I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS
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tended periods may affect product reliability. TABLE 5. CRYSTAL CHARACTERISTICS
TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
IDT™ / ICS™ HCSL CLOCK GENERATOR 5 ICS841608AKI REV. A JUNE 18, 2008 ICS841608I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR TYPICAL PHASE NOISE AT 100MHZ 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz TYPICAL PHASE NOISE AT 125MHZ Filter Raw Phase Noise Data Phase Noise Result by adding Filter to raw data Filter Raw Phase Noise Data Phase Noise Result by adding Filter to raw data
IDT™ / ICS™ HCSL CLOCK GENERATOR 6 ICS841608AKI REV. A JUNE 18, 2008 ICS841608I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power t sk(o) Qy Qx nQy nQx DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME 475Ω Measurement Point33Ω 100Ω 100Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF IREF 3.3V±5% VDD 3.3V±5%, VDDA DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate TSTABLE TSTABLE VRB VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V This load condition is used for I DD , tsk(o), and tjit measurements. 475Ω 50Ω 50Ω HCSL GND SCOPE IREF 3.3V±5% VDD 3.3V±5%, VDDA
IDT™ / ICS™ HCSL CLOCK GENERATOR 7 ICS841608AKI REV. A JUNE 18, 2008 ICS841608I FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED DIFFERENTIAL MESUREMENT POINTS FOR DUTY CYCLE PERIOD SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWINGSINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT nQ Q VCROSS_MAX = 550mV VCROSS_MIN = 250mV VMAX = 1.15V VMIN = -0.30V Q nQ VCROSS_DELTA = 140mV Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) Q - nQ 0.0V COMPOSITE PCIe TRANSFER FUNCTION -20 -40 -60 -80 -100 104 105 106 107 108 -3dB 1.2MHz -3dB 21.9MHz Frequency (Hz) Mag (dB) H3(s) * (H1(s) – H2(s))
This section provides information on power dissipation and junction temperature for the ICS841608I. Equations and example calculations are also provided. = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX ) = 3.465V * (87mA + 15mA) = 353.43mW
- Power (outputs) MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 44.5mW = 356mW Total Power _MAX (3.465V, with all outputs switching) = 353.43mW + 356mW =709.43 mW 2. Junction Temperature. Junction temperature, Tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.709W * 37°C/W = 111.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θθθθθJA FOR 32-PIN VFQFN, FORCED CONVECTION
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. dissipation, use the following equations which assume a 50 Ω load to ground. The highest power dissipation occurs when V DD is HIGH. FIGURE 7. HCSL DRIVER CIRCUIT AND TERMINATION
TABLE 8. θ
TABLE 9. PACKAGE DIMENSIONS this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
TABLE 10. ORDERING INFORMATION reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA