841608 RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Eight HCSL outputs: configurable for PCIe (100MHz) and sRIO (125MHz) clock signals
  • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input
  • Supports the following output frequencies: 100MHz or 125MHz
  • VCO: 500MHz
  • PLL bypass and output enable
  • PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
  • RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.37ps (typical)
  • Full 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package Block Diagram Pin Assignment 841608 32-Lead VFQFPN 5mm x 5mm x 0.925mm package body K Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 XTAL_IN XTAL_OUT MR/nOE V DD nQ0 nQ1 nQ4 VDD nQ3 nQ2 GND FSEL IREF BYPASS V DDA REF_SEL REF_IN VDD GND VDD nQ7 nQ6 GND nQ5 841608 Datasheet FemtoClock® Crystal-to-HCSL Clock Generator

841608 Datasheet

Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics

3 MR/nOE Input Pulldown

internal dividers are reset and the outputs are in high impedance (Hi-Z). When logic LOW, the internal dividers and the outputs are enabled. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3D. 4, 14, 24, 31 VDD Power Core supply pins. 5, 6 Q0, nQ0 Output Differential output pair. HCSL interface levels. 7, 8 Q1, nQ1 Output Differential output pair. HCSL interface levels. 9, 19, 32 GND Power Power supply ground. 10, 11 Q2, nQ2 Output Differential output pair. HCSL interface levels. 12,13 Q3, nQ3 Output Differential output pair. HCSL interface levels. 15, 16 Q4, nQ4 Output Differential output pair. HCSL interface levels. 17, 18 Q5, nQ5 Output Differential output pair. HCSL interface levels. 20, 21 Q6, nQ6 Output Differential output pair. HCSL interface levels. 22, 23 Q7, nQ7 Output Differential output pair. HCSL interface levels. 25 FSEL Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B.

26 IREF Output

current-mode Qx, nQx clock outputs. 27 BYPASS Input Pulldown Selects PLL operation/PLL bypass operation. Asynchronous function. LVCMOS/LVTTL interface levels. See Table 3C. 28 VDDA Power Analog supply pin. 29 REF_SEL Input Pulldown Reference select. Selects the input reference source. LVCMOS/LVTTL interface levels. See Table 3A. 30 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input.

3©2023 Renesas Electronics Corporation January 31, 2023 Table 3A. REF_SEL Function Table Table 3B. FSEL Function Table (fREF = 25MHz) Table 3C. BYPASS Function Table Table 3D. MR/nOE Function Table Input REF_SEL Input Reference

0 XTAL (default)

1 REF_IN

FSEL N Divider Q[0:7], nQ[0:7] 0 5 VCO/5 (100MHz) PCIe (default) 1 4 VCO/4 (125MHz) sRIO Input BYPASS PLL Configuration

0 PLL enabled (default)

1 PLL bypassed (fOUT = fREF/N)

0 Outputs enabled (default)

1 Device reset, outputs disabled (high-impedance)

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

5©2023 Renesas Electronics Corporation January 31, 2023 Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE: All specifications are taken at 100MHz and 125MHz. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: RMS jitter after applying system transfer function. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum limit for PCI Express is 86ps peak-to-peak. NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5-16MHz. See IDT Application Note, PCI Express Reference Clock Requirements. Maximum limit for PCI Express Generation 2 is 3.1ps RMS. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 6: Measurement taken from a differential waveform. NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. NOTE 8: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section. NOTE 9: Measurement taken from a single-ended waveform. NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency VCO/5 100 MHz VCO/4 125 MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 100MHz (1.875MHz – 20MHz) 0.39 ps 125MHz (1.875MHz – 20MHz) 0.37 ps tj Phase Jitter Peak-to-Peak; NOTE 2 100MHz, (1.2MHz – 50MHz 106 Samples, 25MHz Crystal Input 24.36 ps 125MHz, (1.2MHz – 62.5MHz 106 Samples, 25MHz Crystal Input 23.76 ps tREFCLK_HF_RMS Phase Jitter RMS; NOTE 3 100MHz, 106 Samples, 25MHz Crystal Input 2.44 ps 125MHz, 106 Samples, 25MHz Crystal Input 2.37 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 50 ps tsk(o) Output Skew; NOTE 4, 5 105 ps Rise Edge Rate Rising Edge Rate; NOTE 6, 7 0.6 4 V/ns Fall Edge Rate Falling Edge Rate; NOTE 6, 7 0.6 4 V/ns VRB Ringback Voltage; NOTE 6, 8 -100 100 mV VMAX Absolute Maximum Output Voltage; NOTE 9, 10 1150 mV VMIN Absolute Minimum Output Voltage; NOTE 9, 11 -300 mV VCROSS Absolute Crossing Voltage; NOTE 9, 12, 13 250 550 mV VCROSS Total Variation of VCROSS; NOTE 9, 12, 14 140 mV odc Output Duty Cycle; NOTE 6, 15 48 52 % tSTABLE Power-up Stable Clock Output; NOTE 6, 8 500 ps tL PLL Lock Time 90 ms

6©2023 Renesas Electronics Corporation January 31, 2023 NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 14: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 15: Input duty cycle must be 50%.

7©2023 Renesas Electronics Corporation January 31, 2023 Typical Phase Noise at 100MHz Noise Power dBc Hz Offset Frequency (Hz) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps

8©2023 Renesas Electronics Corporation January 31, 2023 Typical Phase Noise at 125MHz Noise Power dBc Hz Offset Frequency (Hz) Filter Phase Noise Result by adding a filter to raw data Raw Phase Noise Data 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.37ps

9©2023 Renesas Electronics Corporation January 31, 2023 Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Output Skew Differential Measurement Points for Rise/Fall Time 3.3V HCSL Output Load AC Test Circuit RMS Phase Jitter Differential Measurement Points for Ringback Measurement Point Measurement Point GND 2pF 2pF IREF VDD VDDA 3.3V±5% 3.3V±5% nQx Qx nQy Qy Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate This load condition is used for IDD, tjit and tsk(o) measurements. 3.3V±5% 3.3V±5% VDD VDDA TSTABLE TSTABLE VRB VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V

10©2023 Renesas Electronics Corporation January 31, 2023 Parameter Measurement Information, continued Single-ended Measurement Points for Delta Cross Point Differential Measurement Points for Duty Cycle/Period Single-ended Measurement Points for Absolute Cross Point/Swing Composite PCIe Transfer Function -20 -40 -60 -80 -100 104 105 106 107 108 -3dB 1.2MHz -3dB 21.9MHz Frequency (Hz) Mag (dB) H3(s) * (H1(s) – H2(s))

resistor can be tied from the REF_IN to ground. should either be left floating or terminated. Figure 1. Power Supply Filtering

chosen to minimize the ppm error. Figure 2. Crystal Input Interface Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface

13©2023 Renesas Electronics Corporation January 31, 2023 Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. Figure 4A. Recommended Termination Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ω impedance. Figure 4A. Recommended Termination

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

Figure 6. 841608 Application Schematic

Equations and example calculations are also provided. The total power dissipation for the 841608 is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.

  • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (87mA + 15mA) = 353.43mW
  • Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 8 * 44.5mW = 356mW Total Power_MAX = (3.465V, with all outputs switching) = 353.43mW + 356mW = 709.43mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature for devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.709W * 37°C/W = 111.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance JA for 32-Pin VFQFPN, Forced Convection

  1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 7. Figure 7. HCSL Driver Circuit and Termination use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD is HIGH.

18©2023 Renesas Electronics Corporation January 31, 2023 Table 8. JA vs. Air Flow Table for a 32 Lead VFQFPN the most current data available.

Ordering Information

Table 10. Ordering Information January 31, 2023 Updated POD link in Package Outline Drawings. March 9, 2020 • Corrected package typo in Ordering Information table.

  • Updated Package Outline Drawings section. May 3, 2016
  • Updated Package Information.
  • Ordering Information Table - deleted tray count and table note.
  • Deleted HiperClocks references through out the datasheet.
  • Deleted “ICS” prefix and “I” suffix in part number.
  • Updated datasheet header/footer.

5.00 ±0.10 5.00 ±0.10 Pin 1 ID TOP VIEWBOTTOM VIEW 25 321 891617 3.15 ±0.15 3.15 ±0.15 24 0.20 0.50 0.40 0.25 (0.525) 0.20 Package Outline 3.15 5.304.20 5.30 3.15 0.250.50 (PCB Top View, NSMD Design) SIDE VIEW RECOMMENDED LAND PATTERN© Renesas Electronics Corporation

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