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841604 REVISION A 4/17/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 841604 is an optimized PCIe and sRIO clock generator. The device uses a 25MHz parallel crystal to generate 100MHz and 125MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suitable to clock components requiring precise and low-jitter PCIe or sRIO or both clock signals. Designed for telecom, networking and industrial applications, the 841604 can also drive the high-speed sRIO and PCIe SerDes clock inputs of communication processors, DSPs, switches and bridges.
FEATURES
Four differential clock outputs: confi gurable for PCIe (100MHz) and sRIO (125MHz) clock signals Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input Supports the following output frequencies: 100MHz or 125MHz VCO: 500MHz PLL bypass and output enable PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant RMS phase jitter, 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.45ps (typical) Full 3.3V power supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 841604 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View REF_SEL REF_IN VDD GND XTAL_IN XTAL_OUT MR/nOE VDD nc nc nc nc GND V DD VDDA BYPASS IREF FSEL VDD nQ3 nQ2 GND nQ1 nQ0 M = ÷20 OSC FemtoClock PLL VCO = 500MHz (default) XTAL_IN XTAL_OUT REF_SEL FSEL MR/nOE IREF BYPASS REF_IN Pulldown Pulldown Pulldown Pulldown Pulldown nQ0 nQ1 nQ2 nQ3
841604 DATA SHEET
2 REVISION A 4/17/15
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1 REF_SEL Input Pulldown Reference select. Selects the input reference source. LVCMOS/LVTTL interface levels. See Table 3D. 2 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input. 4, 13, 19 GND Power Power supply ground.
7 MR/nOE Input Pulldown
function. LVCMOS/LVTTL interface levels. See Table 3C. 15, 16 Q0, nQ0 Output Differential output pair. HCSL interface levels. 17, 18 Q1, nQ1 Output Differential output pair. HCSL interface levels. 20, 21 Q2, nQ2 Output Differential output pair. HCSL interface levels. 22, 23 Q3, nQ3 Output Differential output pair. HCSL interface levels. 25 FSEL Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3A.
26 IREF Output
tial current-mode Qx/nQx clock outputs. MOS/LVTTL interface levels. See Table 3B. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
0 XTAL (default)
1 REF_IN
0 Outputs enabled (default)
1 Device reset, outputs disabled (high-impedance)
0 PLL enabled (default)
1 PLL bypassed (f
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tended periods may affect product reliability. TABLE 5. CRYSTAL CHARACTERISTICS NOTE: Characterized using an 18pF parallel resonant crystal.
4 REVISION A 4/17/15
TABLE 6. AC CHARACTERISTICS, V NOTE: All specifi cations are taken at 100MHz and 125MHz. NOTE 1: Please refer to the Phase Noise Plot. limit for PCI Express is 86ps peak-to-peak. NOTE 3: RMS jitter after applying system transfer function. The pole frequencies for H1 and H2 for PCIe Gen 2 are 8-16MHz and 5 -16MHz. See IDT Application Note, PCI Express Reference Clock Requirements.Maximum limit for PCI Express Generation 2 is 3.1ps rms. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 5: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 6: Measurement taken from differential waveform. NOTE 7: Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). differential zero crossing. See Parameter Measurement Information Section. ±100 differential range. See Parameter Measurement Information Section. NOTE 9: Measurement taken from single ended waveform. NOTE 10: Defi ned as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 11: Defi ned as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 12: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of n Qx. See Parameter Measurement Information Section. NOTE 13: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. for any particular system. See Parameter Measurement Information Section. NOTE 15: Input duty cycle must be 50%.
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TYPICAL PHASE NOISE AT 100MHZ 100MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.36ps (typical) OFFSET FREQUENCY (HZ) NOISE POWER dBc Hz PCIe Filter Raw Phase Noise Data Phase Noise Result by adding a PCIe Filter to raw data OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 125MHZ NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps (typical) PCIe Filter Raw Phase Noise Data Phase Noise Result by adding a PCIe Filter to raw data
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
6 REVISION A 4/17/15
PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME 475Ω Measurement Point33 100Ω 100Ω Measurement Point 49.9Ω 49.9Ω GND 2pF 2pF 0V 0V IREF 3.3V±5% V DD 3.3V±5%, VDDA DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK TSTABLE TSTABLE VRB VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V This load condition is used for I DD , tsk(o), and tjit measurements. 3.3V±5% V DD 3.3V±5%, VDDA
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PARAMETER MEASUREMENT INFORMATION, CONTINUED DIFFERENTIAL MESUREMENT POINTS FOR DUTY CYCLE PERIOD SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING COMPOSITE PCIe TRANSFER FUNCTION -20 -40 -60 -80 -100 104 105 106 107 108 -3dB 1.2MHz -3dB 21.9MHz Frequency (Hz) Mag (dB) H3(s) * (H1(s) – H2(s))
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
8 REVISION A 4/17/15
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 841604 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD and V DDA should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic V DD pin and also shows that V DDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING protection, a 1kΩ resistor can be tied from the REF_IN to ground. pair should either be left fl oating or terminated.
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is shown in Figure 3. The XTAL_OUT pin can be left fl oating. FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE FIGURE 2. CRYSTAL INPUt INTERFACE chosen to minimize the ppm error.
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FIGURE 4. 841604 SCHEMATIC EXAMPLE as possible to the power pin.
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Figure 5A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ω impedance. FIGURE 5A. RECOMMENDED TERMINATION Figure 5B is the recommended termination for applications which require a point to point connection and contain the driver and FIGURE 5B. RECOMMENDED TERMINATION receiver on the same PCB. All traces should all be 50Ω impedance. 0.7V Differential HCSL Clock Driver 0.7V Differential HCSL Clock Driver 0.7V Differential HCSL Add-In Card
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This section provides information on power dissipation and junction temperature for the 841604. Equations and example calculations are also provided. The total power dissipation for the ICS41604I is the sum of the core power plus the analog plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA ) = 3.465V * (87mA + 15mA) = 353.43mW
- Power (outputs) MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 44.5mW = 178mW Total Power _MAX (3.465V, with all outputs switching) = 353.43mW + 178mW = 531.43mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air fl ow and a multi-layer board, the appropriate value is 64.54°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 28-PIN TSSOP, FORCED CONVECTION
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- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. dissipation, use the following equations which assume a 50Ω load to ground. FIGURE 6. HCSL DRIVER CIRCUIT AND TERMINATION
14 REVISION A 4/17/15
TABLE 8. θ
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TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
16 REVISION A 4/17/15
Rev Table Page Description of Change Date Updated data sheet format. 4/17/15
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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.