84150012A

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/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0048/C0057/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0048/C0057 /C0068/C0085/C0065/C0076 /C0074/C0262/C0075 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Wide Operating Voltage Range of 2 V to 6 V /C0068Low Input Current of 1 µA Max /C0068High-Current Outputs Drive Up To

10 LSTTL Loads

/C0068Low Power Consumption, 40-µA Max ICC /C0068Typical tpd = 12 ns /C0068±4-mA Output Drive at 5 V SN54HC109 ...J O R W PACKAGE SN74HC109 . . . D, N, OR NS PACKAGE (TOP VIEW) 1CLR 1CLK 1PRE GND VCC 2CLR 2CLK 2PRE SN54HC109 . . . FK PACKAGE (TOP VIEW) NC − No internal connection 321 2 0 1 9 91 0 1 1 1 2 1 3 NC 2CLK 2PRE 1CLK NC 1PRE 1CLR NC V 2CLR GND NC CC description/ordering information These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC109N SN74HC109N Tube of 40 SN74HC109D −40°C to 85°C SOIC − D Reel of 2500 SN74HC109DR HC109−40 C to 85C SOIC − D Reel of 250 SN74HC109DT HC109 SOP − NS Reel of 2000 SN74HC109NSR HC109 CDIP − J Tube of 25 SNJ54HC109J SNJ54HC109J −55°C to 125°C CFP − W Tube of 150 SNJ54HC109W SNJ54HC109W−55 C to 125C LCCC − FK Tube of 55 SNJ54HC109FK SNJ54HC109FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0048/C0057/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0048/C0057 /C0068/C0085/C0065/C0076 /C0074/C0262/C0075 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCLS470A − MARCH 2003 − REVISED OCTOBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

L LXXX H † H † H H ↑ LLL H H H ↑ H L Toggle H H ↑ LH Q 0 Q 0 H H ↑ HHH L H H L X X Q0 Q 0 † This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK J CLR Q Q C C C C K TG TG TG TG C C C C C C

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0048/C0057/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0048/C0057 /C0068/C0085/C0065/C0076 /C0074/C0262/C0075 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 2) SN54HC109 SN74HC109 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltage VCC = 6 V 4.2 4.2 V VCC = 2 V 0.3 0.5 VIL Low-level input voltage VCC = 4.5 V 0.9 1.35 VVIL Low-level input voltage VCC = 6 V 1.2 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns∆t/∆v Input transition rise/fall time VCC = 6 V 400 400 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0048/C0057/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0048/C0057 /C0068/C0085/C0065/C0076 /C0074/C0262/C0075 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCLS470A − MARCH 2003 − REVISED OCTOBER 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC109 SN74HC109 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 5.9 VVOH VI = VIH or VIL V 2 V 0.002 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 0.1 VVOL VI = VIH or VIL V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 4 80 40 µA C i 2 V to 6 V 3 10 10 10 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC109 SN74HC109 UNITVCC MIN MAX MIN MAX MIN MAX UNIT 2 V 6 4.2 5 fclock Clock frequency 4.5 V 31 21 25 MHzfclock Clock frequency

6 V 36 25 29

2 V 100 150 125

PRE or CLR low 4.5 V 20 30 25 tw Pulse duration PRE or CLR low

6 V 17 25 21

nstw Pulse duration 2 V 80 120 100 ns CLK high or low 4.5 V 16 24 20CLK high or low

6 V 14 20 17

Data (J, K) 4.5 V 20 30 25 tsu Setup time before CLK↑ Data (J, K) nstsu Setup time before CLK↑ 2 V 25 40 30 ns PRE or CLR inactive 4.5 V 5 8 6PRE or CLR inactive

6 V 4 7 5

2 V 0 0 0

th Hold time Data after CLK ↑ 4.5 V 0 0 0 nsth Hold time Data after CLK

6 V 0 0 0

/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0048/C0057/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0048/C0057 /C0068/C0085/C0065/C0076 /C0074/C0262/C0075 /C0080/C0079/C0083/C0073/C0084/C0073/C0086/C0069/C0262/C0069/C0068/C0071/C0069/C0262/C0084/C0082/C0073/C0071/C0071/C0069/C0082/C0069/C0068 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 /C0065/C0078/C0068 /C0080/C0082/C0069/C0083/C0069/C0084 SCLS470A − MARCH 2003 − REVISED OCTOBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC109 SN74HC109 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 6 10 4.2 5 fmax 4.5 V 31 50 21 25 nsfmax

6 V 36 60 25 29

2 V 60 230 345 290

PRE or CLR Q or Q 4.5 V 15 46 69 58 tpd PRE or CLR Q or Q

6 V 12 39 59 49

nstpd 2 V 50 175 250 220 ns CLK Q or Q 4.5 V 15 35 50 44CLK Q or Q

6 V 12 30 42 37

2 V 28 75 110 95

tt Q or Q 4.5 V 8 15 22 19 nstt Q or Q

6 V 6 13 19 16

operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per buffer/driver No load 35 pF

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

www.ti.com 25-Sep-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-8415001VEA ACTIVE CDIP J 16 25 TBD A42 N / A for Pkg Type 5962-8415001VE A SNV54HC109J 5962-8415001VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type 5962-8415001VF A SNV54HC109W 84150012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84150012A SNJ54HC 109FK 8415001EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8415001EA SNJ54HC109J 8415001FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8415001FA SNJ54HC109W JM38510/65304B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65304B2A JM38510/65304BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65304BEA M38510/65304B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 65304B2A M38510/65304BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65304BEA SN54HC109J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC109J SN74HC109D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109

www.ti.com 25-Sep-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74HC109DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109DTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC109N SN74HC109NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC109N SN74HC109NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SN74HC109NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC109 SNJ54HC109FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84150012A SNJ54HC 109FK SNJ54HC109J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8415001EA SNJ54HC109J SNJ54HC109W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8415001FA SNJ54HC109W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

www.ti.com 25-Sep-2013 Addendum-Page 3 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC109, SN54HC109-SP, SN74HC109 :

• Catalog: SN74HC109 , SN54HC109
• Military: SN54HC109
• Space: SN54HC109-SP NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC109DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC109NSR SO NS 16 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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