841484DKILF

Renesas Technology Corp

FemtoClock® Crystal-to-0.7V Differential HCSL Clock Generator 2019

Manufacturer: Renesas Technology Corp

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ICS841484I RENESAS | Alldatasheet

Document overview

Manufacturer or author: RCarroll
PDF pages: 28

Technical content

Features

Four 0.7V differential HCSL outputs: configurable for PCIe (100MHz or 200MHz) and sRIO (125MHz) clock signals
One LVCMOS/LVTTL reference clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input
Supports the following output frequencies: 100MHz, 125MHz, 200MHz or 400MHz
VCO frequency range: 950MHz - 1.25GHz
Configurable spread-spectrum generation for PCIe
PLL bypass and output enable
RMS phase jitter @ 200MHz, using a 25MHz crystal (12kHz – 20MHz): 1.21ps (typical)
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter compliant (REF_OUT disabled)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages M = ÷÷40, ÷÷48 OSC FemtoClock PLL Spread-Spectrum REF_OUT nQ0 nQ1 nQ2 nQ3 Pulldown Pulldown Pulldown Pulldown Pulldown Pullup:Pulldown Pulldown XTAL_IN XTAL_OUT REF_IN OE_REFOUT REF_SEL IREF SSM FSEL[1:0] MR/nOE BYPASS 25MHz 25MHz Block Diagram Pin Assignment 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 XTAL_IN XTAL_OUT MR/nOE VDD nQ0 nQ1 VDD FSEL1 FSEL0 REF_OUT OE_REFOUT GND nc nc GND nQ2 nQ3 VDD nc nc REF_IN REF_SEL VDD VDDA BYPASS IREF SSM GND ICS841484I 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View

ICS841484DKI REVISION A NOVEMBER 7, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 3 MR/nOE Input Pulldown Master reset. LVCMOS/LVTTL interface levels. See Table 3D. 4, 14, 24, 29 V DD Power Core supply pins. 5, 6 Q0, nQ0 Output Differential outp ut pair. HCSL interface levels. 7, 8 Q1, nQ1 Output Differential outp ut pair. HCSL interface levels. 9, 19, 32 GND Power Power supply ground. 10, 11 Q2, nQ2 Output Diffe rential output pair. HCSL interface levels. 12, 13 Q3, nQ3 Output Diffe rential output pair. HCSL interface levels. 15, 16, 17, 18 nc Unused No connect. 20 OE_REFOUT Input Pulldown Output enable pin. LVCM OS/LVTTL interface levels. See Table 3F. Gen 3 applications, the REF_OUT output should be disabled. 22 F_SEL0 Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B. 23 F_SEL1 Input Pullup Output frequency select pin. LV CMOS/LVTTL interface levels. See Table 3B. 25 SSM Input Pulldown Spread-spectrum selection. LV CMOS/LVTTL interface levels. See Table 3A.

26 IREF Output An external fixed precision resistor (475) from this pin to ground provides a

reference current used for differential current-mode Qx, nQx clock outputs. 27 BYPASS Input Pulldown Selects PLL operation/PLL bypass operation. See Table 3C. LVCMOS/LVTTL interface levels. 28 V DDA Power Analog supply pin. 30 REF_SEL Input Pulldown Reference select. Selects the input reference source. LVCMOS/LVTTL interface levels. See Table 3E. 31 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input.

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 3 ©2012 Integrated Device Technology, Inc. Function Tables Table 3A. Spread-Spectrum Modulation (SSM) Function Table (fREF = 25MHz) Table 3B. FSEL Function Table (fREF = 25MHz) Table 3C. BYPASS Function Table Table 3D. MR/nOE Function Table NOTE 1: Asynchronous Function Table 3E. REF_SEL Function Table Table 3F. OE_REFOUT Function Table Input Outputs SSM Q[0:3], nQ[0:3]

0 SSM off (default)

1 SSM on (typical: 32kHz, -0.5%) See Table 6B Inputs Outputs FSEL1 FSEL0 M Divider N Di vider Q[0:3], nQ[0:3] 0 0 48 12 VCO/12 (100MHz) PCIe 0 1 40 8 VCO/8 (125MHz) sRIO 1 0 48 6 VCO/6 (200MHz) PCIe (default) 1 1 48 3 VCO/3 (400MHz) Input BYPASS PLL Configuration

0 PLL on (default)

1 PLL bypassed (Q[0:3], nQ[0:3] = f REF/N)

0 Outputs enabled (default)

1 Device reset, outputs disabled (High Impedance)

REF_SEL Input Reference

0 XTAL (default)

1R E F _ I N Input OE_REFOUT Function

0 REF_OUT disabled (Hig h Impedance) (default)

1 REF_OUT enabled

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 4 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 33.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.16 3.3 V DD V IDD Power Supply Current Outputs unterminated 156 mA IDDA Analog Supply Current Outputs unterminated 16 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current REF_IN, REF_SEL, BYPASS, SSM, F_SEL0, MR/nOE, OE_REFOUT V DD = VIN = 3.465V 150 µA F_SEL1 V DD = VIN = 3.465V 5 µA IIL Input Low Current REF_IN, REF_SEL, BYPASS, SSM, F_SEL0, MR/nOE, OE_REFOUT V DD = 3.465V, VIN = 0V -5 µA F_SEL1 V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage REF_OUT I OH = -12mA 2.6 V VOL Output Low Voltage REF_OUT I OL = 12mA 0.5 V

ICS841484DKI REVISION A NOVEMBER 7, 2012 5 ©2012 Integrated Device Technology, Inc. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal. has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE: PCIe jitter parameters were obtained with Spread Spectum Modulation disabled. NOTE: PCIe Gen 2 and Gen 3 jitter parameters were obtained with REF_OUT disabled. (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 6 ©2012 Integrated Device Technology, Inc. Table 6B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTES continued on next page. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency Q[0:3], nQ[0:3]

100 MHz

125 MHz

200 MHz

400 MHz

REF_OUT 25 MHz f IN Input Frequency REF_IN REF_SEL = 1, BYPASS = 0 25 MHz tsk(o) Output Skew; NOTE 1, 2 70 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 fOUT = 100MHz, N = 12, OE_REFOUT = 1,SSM = 0 60 100 ps fOUT = 125MHz, N = 8, OE_REFOUT = 1, SSM = 0 35 92 ps fOUT = 200MHz, N = 6, OE_REFOUT = 1, SSM = 0 20 72 ps fOUT = 400MHz, N = 3, OE_REFOUT = 1, SSM = 0 15 36 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 3 fOUT = 100MHz (12kHz – 20MHz) 1.21 1.6 ps fOUT = 125MHz (12kHz – 20MHz) 1.47 1.6 ps fOUT = 200MHz (12kHz – 20MHz) 1.23 1.6 ps fOUT = 400MHz (12kHz – 20MHz) 1.32 2 ps tL PLL Lock Time 85 ms VMAX Absolute Maximum Output Voltage; NOTE 4, 5 1150 mV VMIN Absolute Minimum Output Voltage; NOTE 4, 6 -300 mV VRB Ringback Voltage; NOTE 7, 8 -100 100 mV tSTABLE Time before VRB is allowed; NOTE 7, 8 500 ps FM SSC Modulation Frequency; NOTE 9 29 32 33.33 kHz FMF SSC Modulation Factor; NOTE 9 -0.5 % SSCRED Spectral Reduction; NOTE 9 10 dB VCROSS Absolute Crossing Voltage; NOTE 4, 10, 11 125 560 mV VCROSS Total Variation of VCROSS; NOTE 4, 10, 12 140 mV tSLEW + tSLEW - Rising/Falling Edge Rate; NOTE 7, 13 Measured between -150mV to +150mV 0.6 4.7 V/ns tR / tF Output Rise/Fall Time REF_OUT 690 1550 ps odc Output Duty Cycle REF_OUT; NOTE 14 Using REF_IN Input 48 52 %

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 7 ©2012 Integrated Device Technology, Inc. NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: Measurement taken from single-ended waveform. NOTE 5: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 6: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 7: Measurement taken from a differential waveform. NOTE 8: T STABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section. NOTE 9: Spread Spectrum clocking enabled. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section. NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the V CROSS for any particular system. See Parameter Measurement Information Section. NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. NOTE 14: REF_OUT duty cycle characterized with REF_IN input duty cycle between 48% and 52%.

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 8 ©2012 Integrated Device Technology, Inc. Typical Phase Noise at 100MHz Typical Phase Noise at 125MHz Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 9 ©2012 Integrated Device Technology, Inc. Typical Phase Noise at 200MHz Typical Phase Noise at 400MHz Noise Power dBc Hz Offset Frequency (Hz) Noise Power dBc Hz Offset Frequency (Hz)

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 10 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit 3.3V LVCMOS Output Load AC Test Circuit Cycle-to-Cycle Jitter 3.3V HCSL Output Load AC Test Circuit Output Skew RMS Phase Jitter 475Ω Measurement Point33Ω 50Ω 50Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF IREF VDD VDDA 3.3V±5% 3.3V±5% This load condition is used for VMAX , VMIN, VRB, tSTABLE, VCROSS, VCROSS and tSLEW± measurements. SCOPE Qx GND VDD VDDA 1.65V±5% 1.65V±5% -1.65V±5% nQ0:nQ3 Q0:Q3 ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

475 50 50 GND SCOPE IREF 3.3V±5% VDDA 3.3V±5% VDD This load condition is used for IDD, tjit(cc), tsk(o), odc and tjit(Ø) measurements. nQx Qx nQy Qy tsk(o) Offset Frequencyf1 f2 Phase Noise Plot Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter = Noise Power 2 * * ƒ 1 *

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 11 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information, continued LVCMOS Output Duty Cycle Single-ended Measurement Points for Absolute Cross Point/Swing Differential Measurement Points for Ringback LVCMOS Rise/Fall Time Single-ended Measurement Points for Delta Cross Point Differential Measurement Points for Duty Cycle/Period tPERIOD tPW tPERIOD odc = VDD x 100% tPW REF_OUT VCROSS_MAX VCROSS_MIN VMAX VMIN nQ Q TSTABLE VRB Q - nQ -150mV VRB = -100mV VRB = +100mV +150mV 0.0V VRB TSTABLE 20% 80% 80% 20% tR tF REF_OUT VCROSS nQ Q Q - nQ 0.0V Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential)

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 12 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information, continued Differential Measurement Points for Rise/Fall Edge Rate PLL Locktime Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 14 ©2012 Integrated Device Technology, Inc. Applications Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. REF_IN For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. Crystal Input For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. Outputs: LVCMOS Output The unused LVCMOS output can be left floating. There should be no trace attached. Differential Outputs All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

ICS841484DKI REVISION A NOVEMBER 7, 2012 16 ©2012 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 18 ©2012 Integrated Device Technology, Inc. PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements.

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 19 ©2012 Integrated Device Technology, Inc. Schematic Example Figure 5 (next page) shows an example of ICS841484I application schematic. In this example, the device is operated at VDD = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS841484I provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set.

25 MHz

ICS841484DKI REVISION A NOVEMBER 7, 2012 21 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS841484I. Equations and example calculations are also provided. The total power dissipation for the ICS841484I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection

Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pairs. HCSL output driver circuit and termination are shown in Figure 6. Figure 6. HCSL Driver Circuit and Termination use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX.

Type A: Chamfer on the paddle (near pin 1)
Type C: Mouse bite on the paddle (near pin 1)

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR ICS841484DKI REVISION A NOVEMBER 7, 2012 26 ©2012 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A T6B T10 AC Characteristics Table, Output Duty Cycle - corrected typo from Q[0:1], nQ[0:1] to Q[0:3], nQ[0:3]. Ordering Information Table - deleted tray count. 7/6/2012 A 4A 4 I DD, IDDA; Test Conditions; added "Outputs Unterminated" 11/7/12

ICS841484I Data Sheet FEMTOCLOCK ® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without re presentation or warranty of a ny kind, whether express or implie d, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signif- icantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.

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Product Information

841484DKILF specifications and overview.

Summary

FemtoClock® Crystal-to-0.7V Differential HCSL Clock Generator 2019

Description

FemtoClock® Crystal-to-0.7V Differential HCSL Clock Generator 2019

Source title 841484DKILF Datasheet(PDF) - Renesas Technology Corp

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