HM-65262 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

Features

  • TTL Compatible Inputs and Outputs
  • JEDEC Approved Pinout
  • No Clocks or Strobes Required oC to +125oC
  • Equal Cycle and Access Time
  • Single 5V Supply
  • Gated Inputs-No Pull-Up or Pull-Down Resistors Required

Description

The HM-65262 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262 is available in both JEDEC standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high board- level packing density. Gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resis- tors. The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temper- ature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices. Pinouts

Ordering Information

PACKAGE TEMP. RANGE 70ns/20 µA (NOTE 1) 85ns/20µA (NOTE 1) (NOTE 1) 85ns/400µA PKG. NO. CERDIP -40 oC to +85oC HM1-65262B-9 HM1-65262-9 - F20.3 JAN # -55 oC to +125oC 29109BRA 29103BRA - F20.3 SMD# -55 oC to +125oC 8413203RA 8413201RA - F20.3 CLCC (SMD#) -55 oC to +125oC 8413203YA 8413201YA - J20.C NOTE: 1. Access Time/Data Retention Supply Current. HM-65262 (CERDIP) TOP VIEW HM-65262 (CLCC) TOP VIEW 1A0 Q W GND VCC A12 A11 A10 A13 D E 91 0 1 1 1 2 22 011 9 VCC A13 Q A12 A11 A10 W GND E D A0 - A13 Address Input E Chip Enable/Power Down Q Data Out D Data In VSS /GND Ground VCC Power (+5) W Write Enable File Number 3002.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

128 X 128

A A ROW DECODER (1 OF 128)A4 COLUMN DECODER (1 OF 128) AND I / O CIRCUITRY Q W E D A10 A11 COLUMN ADDRESS BUFFERS HM-65262

Absolute Maximum Ratings Thermal Information Thermal Resistance (Typical) θ JA θJC Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX ICCSB1 Standby Supply Current -od 50 µA HM-65262B-9, HM-65262-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V - 900 µA HM-65262C-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V ICCSB Standby Supply Current - 5 mA E = 2.2V, IO = 0mA, VCC = 5.5V ICCEN Enabled Supply Current - 50 mA E = 0.8V, IO = 0mA, VCC = 5.5V ICCOP Operating Supply Current (Note 1) - 50 mA E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V ICCDR Data Retention Supply Current - 20 µA HM-65262B-9, HM-65262-9, VCC = 2.0V,E = VCC - 400 µA HM-65262C-9, V CC = 2.0V,E = VCC ICCDR1 Data Retention Supply Current - 30 µA HM-65262B-9, HM-65262-9, VCC = 3.0V,E = VCC - 550 µA HM-65262C-9, V CC = 3.0V,E = VCC VCCDR Data Retention Supply Voltage 2.0 - V II Input Leakage Current -1.0 +1.0 µA VI = V CC or GND, VCC = 5.5V IOZ Output Leakage Current -1.0 +1.0 µA VIO = V CC or GND, VCC = 5.5V VIL Input Low Voltage -0.3 0.8 V V CC = 4.5V VIH Input High Voltage 2.2 V CC +0.3 V V CC = 5.5V VOL Output Low Voltage - 0.4 V IO = 8.0mA, V CC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -4.0mA, V CC = 4.5V VOH2 Output High Voltage (Note 2) V CC -0.4 - V IO = -100 µA, VCC = 4.5V Capacitance TA = +25oC SYMBOL PARAMETER MAX UNITS TEST CONDITIONS CI Input Capacitance (Note 2) 10 pF f = 1MHz, All measurements are referenced to device GNDCIO Input/Output Capacitance (Note 2) 12 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP . 2. Tested at initial design and after major design changes. HM-65262

HM-65262B-9 HM-65262-9 HM-65262C-9 MIN MAX MIN MAX MIN MAX READ CYCLE (1) TAVAX Read/Cycle Time 70 - 85 - 85 - ns (Notes 1, 3) (2) TAVQV Address Access Time - 70 - 85 - 85 ns (Notes 1, 3) (3) TELQV Chip Enable Access Time - 70 - 85 - 85 ns (Notes 1, 3) (4) TELQX Chip Enable Output Enable Time 5-5-5- n s (Notes 2, 3) (5) TEHQX Chip Disable Output Hold Time 5-5-5- n s (Notes 2, 3) (6) TAXQX Address Invalid Output Hold Time 5-5-5- n s (Notes 2, 3) (7) TEHQZ Chip Enable Output Disable Time -3 0-3 0-3 0 n s (Notes 2, 3) WRITE CYCLE (8) TAVAX Write Cycle Time 70 - 85 - 85 - ns (Notes 1, 3) (9) TELWH Chip Selection to End of Write 55 - 65 - 65 - ns (Notes 1, 3) (10) TWLWH Write Enable Pulse Width 40 - 45 - 45 - ns (Notes 1, 3) (11) TAVWL Address Setup Time 0 - 0 - 0 - ns (Notes 1, 3) (12) TWHAX Address Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (13) TDVWH Data Setup Time 30 - 35 - 35 - ns (Notes 1, 3) (14) TWHDX Data Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (15) TWLQZ Write Enable Output Disable Time -3 0-3 0-3 0 n s (Notes 2, 3) (16) TWHQX Write Disable Output Enable Time 0-0-0- n s (Notes 2, 3) (17) TAVWH Address Valid to End of Write 55 - 65 - 65 - ns (Notes 1, 3) (18) TAVEL Address Setup Time 0 - 0 - 0 - ns (Notes 1, 3) (19) TEHAX Address Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (20) TAVEH Address Valid to End of Write 55 - 65 - 65 - ns (Notes 1, 3) (21) TELEH Enable Pulse Width 55 - 65 - 65 - ns (Notes 1, 3) (22) TWLEH Write Enable Pulse Setup Time 40 - 45 - 45 - ns (Notes 1, 3) (23) TDVEH Chip Setup Time 30 - 35 - 35 0 ns (Notes 1, 3) (24) TEHDX Data Hold Time 0 - 0 - 0 - ns (Notes 1, 3) NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF , access time is derated by 0.15ns per pF . 2. Tested at initial design and after major design changes. 3. V CC = 4.5 and 5.5V. HM-65262

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

1130 Brussels, Belgium

FIGURE 6. TYPICAL ICCDR vs TA