SN54HC151 TI | Alldatasheet
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/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0053/C0049/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0053/C0049 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0262/C0076/C0073/C0078/C0069 /C0068/C0065/C0084/C0065 /C0083/C0069/C0076/C0069/C0067/C0084/C0079/C0082/C0083/C0047/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0083 SCLS110E − DECEMBER 1982 − REVISED SEPTEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Wide Operating Voltage Range of 2 V to 6 V /C0068Outputs Can Drive Up To 10 LSTTL Loads /C0068Low Power Consumption, 80-µA Max ICC /C0068Typical tpd = 13 ns /C0068±6-mA Output Drive at 5 V /C0068Low Input Current of 1 µA Max /C00688-Line to 1-Line Multiplexers Can Perform as: − Boolean-Function Generators − Parallel-to-Serial Converters − Data Source Selectors Y W G GND VCC A B C SN54HC151 ...J O R W PACKAGE SN74HC151 . . . D, N, NS, OR PW PACKAGE (TOP VIEW) 321 2 0 1 9 91 01 11 21 3 NC A NC Y W NC C B V G GND NC SN54HC151 . . . FK PACKAGE (TOP VIEW) CC NC − No internal connection description/ordering information These data selectors/multiplexers provide full binary decoding to select one of eight data sources. The strobe (G) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC151N SN74HC151N Tube of 40 SN74HC151D SOIC − D Reel of 2500 SN74HC151DR HC151 −40°C to 85°C SOIC − D Reel of 250 SN74HC151DT HC151 −40°C to 85°C SOP − NS Reel of 2000 SN74HC151NSR HC151 Tube of 90 SN74HC151PW TSSOP − PW Reel of 2000 SN74HC151PWR HC151TSSOP − PW Reel of 250 SN74HC151PWT HC151 CDIP − J Tube of 25 SNJ54HC151J SNJ54HC151J −55°C to 125°C CFP − W Tube of 150 SNJ54HC151W SNJ54HC151W−55 C to 125C LCCC − FK Tube of 55 SNJ54HC151FK SNJ54HC151FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0053/C0049/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0053/C0049 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0262/C0076/C0073/C0078/C0069 /C0068/C0065/C0084/C0065 /C0083/C0069/C0076/C0069/C0067/C0084/C0079/C0082/C0083/C0047/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0083 SCLS110E − DECEMBER 1982 − REVISED SEPTEMBER 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D0, D1. . . D7 = the level of the respective D input
/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0053/C0049/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0053/C0049 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0262/C0076/C0073/C0078/C0069 /C0068/C0065/C0084/C0065 /C0083/C0069/C0076/C0069/C0067/C0084/C0079/C0082/C0083/C0047/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0083 SCLS110E − DECEMBER 1982 − REVISED SEPTEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) Y TG TG TG TG TG TG TG TG Pin numbers shown are for the D, J, N, NS, PW, and W packages. G A B C
/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0053/C0049/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0053/C0049 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0262/C0076/C0073/C0078/C0069 /C0068/C0065/C0084/C0065 /C0083/C0069/C0076/C0069/C0067/C0084/C0079/C0082/C0083/C0047/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0083 SCLS110E − DECEMBER 1982 − REVISED SEPTEMBER 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC151 SN74HC151 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltage VCC = 6 V 4.2 4.2 V VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VVIL Low-level input voltage VCC = 6 V 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns∆t/∆v Input transition rise/fall time VCC = 6 V 400 400 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0083/C0078/C0053/C0052/C0072/C0067/C0049/C0053/C0049/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0049/C0053/C0049 /C0056/C0262/C0076/C0073/C0078/C0069 /C0084/C0079 /C0049/C0262/C0076/C0073/C0078/C0069 /C0068/C0065/C0084/C0065 /C0083/C0069/C0076/C0069/C0067/C0084/C0079/C0082/C0083/C0047/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0083 SCLS110E − DECEMBER 1982 − REVISED SEPTEMBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC151 SN74HC151 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 5.9 VVOH VI = VIH or VIL V 2 V 0.002 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 0.1 VVOL VI = VIH or VIL V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA C i 2 V to 6 V 3 10 10 10 pF switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC151 SN74HC151 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT
2 V 94 250 360 312
A, B, or C Y or W 4.5 V 30 50 73 63A, B, or C Y or W
6 V 25 43 62 54
2 V 74 195 283 244
tpd Any D Y or W 4.5 V 23 39 57 49 nstpd Any D Y or W
6 V 20 33 48 41
2 V 49 127 185 159
G Y or W 4.5 V 15 25 37 32G Y or W
6 V 13 22 32 28
2 V 22 75 110 95
tt Y or W 4.5 V 9 15 22 19 nstt Y or W
6 V 8 13 19 16
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2 V 107 350 525 440
6 V 30 59 89 76
2 V 90 275 415 345
6 V 25 47 72 59
2 V 67 205 310 255
6 V 18 35 53 43
2 V 51 210 315 265
6 V 14 36 53 45
NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 84128012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 8412801EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type SN54HC151J ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type SN74HC151D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC151NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC151NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC151PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC151FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type SNJ54HC151J ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1
(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 2
MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96
28 TERMINAL SHOWN
B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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