8410001DA

SN54HC393 TI | Alldatasheet

Document overview

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Technical content

SNx4HC393 Dual 4-Bit Binary Counters

1 Features

Wide operating voltage range of 2V to 6V
Outputs can drive up to 10 LSTTL loads
Low power consumption: 80μA max ICC
Typical tpd = 13ns
±4mA output drive at 5V
Low input current of 1μA max
Dual 4-bit binary counters with individual clocks
Direct clear for each 4-bit counter
Can significantly improve system densities by reducing counter package count by 50%

2 Description

The ’HC393 devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) SNx4HC393 D (SOIC, 14) 8.65 mm x 6mm 8.65 mm x 3.9 mm N (PDIP, 14)) 19.3mm x 9.4mm 19.3mm x 6.35mm NS (SOP, 14) 10.3 mm x 7.8mm 10.3 mm x 5.3 mm DB (SSOP, 14) 6.2 mm x 7.8mm 6.2 mm x 5.3 mm PW (TSSOP, 14) 5 mm x 6.4mm 5 mm x 4.4 mm DYY (SOT-23, 14) 4.2mm x 3.26mm 4.2mm x 2mm J (CDIP, 14) 19.55mm x 7.9mm 19.55 mm x 6.7mm W (CFP, 14) 9.21mm x 9 mm 9.21mm x 6.28mm FK (LCCC, 14) 8.9mm x 8.9mm 8.9mm x 8.9mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. Logic Diagram, Each Counter (Positive Logic) SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 www.ti.com

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3 Pin Configuration and Functions

SN54HC393 J or W Package, 14-Pin CDIP or CFP; SN74HC393 D, DB, DYY, N, NS, or PW Package; 14- Pin SOIC, SSOP, SOT-23, TVSOP, SOP, or TSSOP (Top View) A. NC - No internal connection (Top View) Table 3-1. Pin Functions PIN TYPE1 DESCRIPTION NAME NO. 1CLK 1 I Counter 1 Clock Input 1CLR 2 I Counter 1 Clear Input 1QA 3 O Counter 1 A Output 1QB 4 O Counter 1 B Output 1QC 5 O Counter 1 B Output 1QD 6 O Counter 1 B Output GND 7 G Ground 2QD 8 O Counter 2 D Output 2QC 9 O Counter 2 C Output 2QB 10 O Counter 2 B Output 2QA 11 O Counter 2 A Output 2CLR 12 I Counter 2 Clear Input 2CLK 13 I Counter 2 Clock Input VCC 14 P VCC 1. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. www.ti.com SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN54HC393 SN74HC393

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range -0.5 7 V IIK Input clamp current(2) For VI < 0 V or VI > VCC ±20 mA IOK Output clamp current(2) For VO < 0 V or VO > VCC ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous current through VCC or GND ±50 mA Tstg Storage temperature range -65 150 ℃ (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) SN54HC393 SN74HC393 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 2 5 6 2 5 6 V VIH High-level input voltage VCC = 2 V 1.5 1.5 VVCC = 4.5 V 3.15 3.15 VCC = 6 V 4.2 4.2 VIL Low-level input voltage VCC = 2 V 0.5 0.5 VVCC = 4.5 V 1.35 1.35 VCC = 6 V 1.8 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V Δt/Δv(2) Input transition rise/fall time VCC = 2 V 1000 1000 nsVCC = 4.5 V 500 500 VCC = 6 V 400 400 TA Operating free-air temperature -55 125 -40 85 ℃ (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (2) If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

4.3 Thermal Information

THERMAL METRIC(1) SN74HC393 UNITD (SOIC) DB (SSOP) DYY (SOT-23) N (PDIP) NS (SO) PW (TSSOP)

14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 86 96 124.1 80 76 113 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 www.ti.com

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4.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25℃ SN54HC393 SN74HC393 UNIT MIN TYP MAX MIN MAX MIN MAX VOH VI = VIH or VIL IOH = -20 μA 2 V 1.9 1.998 1.9 1.9 V 6 V 5.9 5.999 5.9 5.9 VOL VI = VIH or VIL IOL = 20 μA 2 V 0.002 0.1 0.1 0.1 V 6 0.001 0.1 0.1 0.1 II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0 IO = 0 6 V 8 160 80 μA Ci 2 V to 6 V 3 10 10 10 pF

4.5 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC TA = 25℃ SN54HC393 SN74HC393 UNIT MIN MAX MIN MAX MIN MAX fclock Clock frequency 2 V 6 4.2 5 MHz4.5 V 31 21 25

6 V 36 25 28

2 V 80 120 100

4.5 V 16 24 20

6 V 14 20 18

tsu Setup time, CLR inactive

2 V 25 25 25

ns4.5 V 5 5 5

6 V 5 5 5

4.6 Switching Characteristics

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (Figure 5-1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25℃ SN54HC393 SN74HC393 UNIT MIN TYP MAX MIN MAX MIN MAX f max CLK QA 2 V 6 10 4.2 5 MHz4.5 V 31 50 21 25

6 V 36 60 25 28

2 V 50 120 180 150

4.5 V 15 24 36 30

6 V 13 20 31 26

2 V 72 190 285 240

4.5 V 22 38 57 47

6 V 18 32 48 40

2 V 91 240 360 300

4.5 V 28 48 72 60

6 V 22 41 61 51

2 V 100 290 430 360

4.5 V 32 58 87 72

6 V 24 50 74 62

2 V 45 165 250 205

4.5 V 17 33 49 41

6 V 14 28 42 35

2 V 28 75 110 95

ns4.5 V 8 15 22 19

6 V 6 13 19 16

4.7 Operating Characteristics

TA = 25℃ PARAMETER TEST CONDITIONS TYP UNIT CPD Power dissipation capacitance No load 40 pF SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 www.ti.com

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5 Parameter Measurement Information

A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 5-1. Load Circuit and Voltage Waveforms www.ti.com SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN54HC393 SN74HC393

6 Detailed Description

6.1 Overview

The ’HC393 devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ’HC393 devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

6.2 Functional Block Diagram

Figure 6-1. Logic Diagram, Each Counter (Positive Logic) SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 www.ti.com

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6.3 Device Functional Modes

Table 6-1. Function Table Count Sequence (Each Buffer) COUNT OUTPUTS QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1 μF and 1μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

7.2 Layout

7.2.1 Layout Guidelines

Bypass capacitor placement – Place near the positive supply terminal of the device – Provide an electrically short ground return path – Use wide traces to minimize impedance – Keep the device, capacitors, and traces on the same side of the board whenever possible
Signal trace geometry – 8mil to 12mil trace width – Lengths less than 12cm to minimize transmission line effects – Avoid 90° corners for signal traces – Use an unbroken ground plane below signal traces – Flood fill areas around signal traces with ground – For traces longer than 12cm
Use impedance controlled traces
Source-terminate using a series damping resistor near the output
Avoid branches; buffer signals that must branch separately

7.2.2 Layout Example

≥ W W W ≥ 5W WORST BETTER BEST Figure 7-1. Example Trace Corners for Improved Signal Integrity SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 www.ti.com

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

8.1 Documentation Support

8.1.1 Related Documentation

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (July 2003) to Revision E (December 2024) Page

Added Device Information table, Pin Functions table, Thermal Information table, Device Functional Modes,Application and Implementation section, Device and Documentation Support section, and Mechanical,
Added DYY package to Device Information table, Pin Functions and Configuration section, and Thermal

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN54HC393, SN74HC393 SCLS143E – DECEMBER 1982 – REVISED DECEMBER 2024 www.ti.com

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www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 84100012A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 84100012A SNJ54HC 393FK 8410001CA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8410001CA SNJ54HC393J 8410001DA Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8410001DA SNJ54HC393W JM38510/66309BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 66309BCA JM38510/66309BCA.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 66309BCA M38510/66309BCA Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/ 66309BCA SN54HC393J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC393J SN54HC393J.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC393J SN74HC393D Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC393 SN74HC393DBR Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393DBR.A Active Production SSOP (DB) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393DR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393DR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393DT Obsolete Production SOIC (D) | 14 - - Call TI Call TI -40 to 85 HC393 SN74HC393N Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC393N SN74HC393N.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC393N SN74HC393NSR Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393NSR.A Active Production SOP (NS) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393PW Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -40 to 85 HC393 SN74HC393PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393PWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393PWR1G4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC393 SN74HC393PWT Obsolete Production TSSOP (PW) | 14 - - Call TI Call TI -40 to 85 HC393 Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SN74HCS393DYYR Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 HCS393 SN74HCS393DYYR.A Active Production SOT-23-THIN (DYY) | 14 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 HCS393 SNJ54HC393FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 84100012A SNJ54HC 393FK SNJ54HC393FK.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 84100012A SNJ54HC 393FK SNJ54HC393J Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8410001CA SNJ54HC393J SNJ54HC393J.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8410001CA SNJ54HC393J SNJ54HC393W Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8410001DA SNJ54HC393W SNJ54HC393W.A Active Production CFP (W) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 8410001DA SNJ54HC393W (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 2

www.ti.com 7-Oct-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC393, SN74HC393 :

Catalog : SN74HC393
Military : SN54HC393 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant SN74HCS393DYYR SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC393DBR SSOP DB 14 2000 353.0 353.0 32.0 SN74HC393DR SOIC D 14 2500 353.0 353.0 32.0 SN74HC393NSR SOP NS 14 2000 353.0 353.0 32.0 SN74HC393NSR SOP NS 14 2000 353.0 353.0 32.0 SN74HC393PWR TSSOP PW 14 2000 356.0 356.0 35.0 SN74HC393PWR1G4 TSSOP PW 14 2000 356.0 356.0 35.0 SN74HCS393DYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 30-Oct-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 84100012A FK LCCC 20 55 506.98 12.06 2030 NA 8410001DA W CFP 14 25 506.98 26.16 6220 NA SN74HC393N N PDIP 14 25 506 13.97 11230 4.32 SN74HC393N N PDIP 14 25 506 13.97 11230 4.32 SN74HC393N.A N PDIP 14 25 506 13.97 11230 4.32 SN74HC393N.A N PDIP 14 25 506 13.97 11230 4.32 SNJ54HC393FK FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC393FK.A FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC393W W CFP 14 25 506.98 26.16 6220 NA SNJ54HC393W.A W CFP 14 25 506.98 26.16 6220 NA Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.38 0.22 8.2

7.4 TYP

0.05 MIN

0.25 GAGE PLANE 0 -8

2 MAX

0.25 0.09 B 5.6 5.0 NOTE 4 A 6.5 5.9 NOTE 3 0.95 0.55 SSOP - 2 mm max heightDB0014A SMALL OUTLINE PACKAGE 4220762/A 05/2024

0.15 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

14X (1.85) 14X (0.45) 12X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0014A SMALL OUTLINE PACKAGE 4220762/A 05/2024 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.85) 14X (0.45) 12X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0014A SMALL OUTLINE PACKAGE 4220762/A 05/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.3 0.11

1.1 MAX

C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 4X 4° - 15° 4X 0° - 15°

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/D 07/2024 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Summary

SNx4HC393 Dual 4-Bit Binary Counters REVISED DECEMBER 2024

Description

SNx4HC393 Dual 4-Bit Binary Counters REVISED DECEMBER 2024

Source title 8410001DA Datasheet(PDF) - Texas Instruments

Read 8410001DA online.

SN54HC393 TI | Alldatasheet

Document overview

Technical content

1 Features

2 Description

10 Mechanical, Packaging, and Orderable

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

3 Pin Configuration and Functions

4 Specifications

4.1 Absolute Maximum Ratings

4.2 Recommended Operating Conditions

4.3 Thermal Information

14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

4.4 Electrical Characteristics

4.5 Timing Requirements

6 V 36 25 28

2 V 80 120 100

4.5 V 16 24 20

6 V 14 20 18

2 V 25 25 25

6 V 5 5 5

4.6 Switching Characteristics

6 V 36 60 25 28

2 V 50 120 180 150

4.5 V 15 24 36 30

6 V 13 20 31 26

2 V 72 190 285 240

4.5 V 22 38 57 47

6 V 18 32 48 40

2 V 91 240 360 300

4.5 V 28 48 72 60

6 V 22 41 61 51

2 V 100 290 430 360

4.5 V 32 58 87 72

6 V 24 50 74 62

2 V 45 165 250 205

4.5 V 17 33 49 41

6 V 14 28 42 35

2 V 28 75 110 95

6 V 6 13 19 16

4.7 Operating Characteristics

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

5 Parameter Measurement Information

6 Detailed Description

6.1 Overview

6.2 Functional Block Diagram

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

6.3 Device Functional Modes

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H

7 Application and Implementation

7.1 Power Supply Recommendations

7.2 Layout

7.2.1 Layout Guidelines

7.2.2 Layout Example

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

8 Device and Documentation Support

8.1 Documentation Support

8.1.1 Related Documentation

8.2 Receiving Notification of Documentation Updates

8.3 Support Resources

8.4 Trademarks

8.5 Electrostatic Discharge Caution