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Technical content
Features
- Five single-ended LVCMOS/LVTTL outputs
- Two REF_OUT LVCMOS/LVTTL clock outputs
- Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference input
- Supports the following output frequencies: Output QAA/Bank B: 33.33MHz, 50MHz, 66.67MHz, 83.33MHz, 100MHz, 125MHz, 133.33MHz and 166.67MHz Output QAB: 125MHz
- VCO frequency: 2GHz
- Slew rate control
- Voltage supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package 840S07I 32-Lead TQFP, E-Pad 7mm x 7mm x1mm package body Y Package Top View Pin Assignment Block Diagram 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 VDDA VDD XTAL_OUT XTAL_IN GND REF_SEL REF_IN F_SELB2 GND QAA VDDO_AA GND QB0 QB1 QB2 VDDO_B nOE_REF VDDO_REF REF_OUT0 REF_OUT1 GND F_SELB1 MR/nOE F_SELB0 SLEW1 SLEW0 F_SELAA1 F_SELAA0 GND QAB VDDO_AB F_SELAA2 PLL VCO 2GHz M = ÷80 ÷NAA NAB ÷16 ÷NB OSC QAA QAB QB0 QB1 QB2 REF_OUT0 REF_OUT1 SLEW[1:0] REF_IN REF_SEL XTAL_IN XTAL_OUT 25MHz 25MHz Pulldown MR/nOE Pulldown Pulldown Pulldown Pulldown [2, 1] Pulldown, [0] Pullup nOE_REF F_SELB[2:0] F_SELAA[2:0] Pullup 125MHz 840S07I Data Sheet Crystal-to-LVCMOS/LVTTL Frequency Synthesizer
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1V DDA Power Analog supply pin. 2V DD Power Core supply pin. XTAL_IN Input Crystal oscillator inte rface. XTAL_IN is the input. XTAL_OUT is the output. 21, 24, 27 GND Power Power supply ground. crystal. See Table 3D. LVCMOS/LVTTL interface levels. 7 REF_IN Input Pulldown Single-ended reference clock input. Table 3B. LVCMOS/LVTTL interface levels. Input Pulldown Frequency select pins for Bank B outputs. See Table 3C. LVCMOS/LVTTL interface levels. 9 nOE_REF Input Pullup Active low REF_OUT enable/disable pin. See Table 3F. LVCMOS/LVTTL interface levels. 10 V DDO_REF Power Output supply pin for REF_OUTx clock outputs. REF_OUT1 Output Single-ended reference clock output s. LVCMOS/LVTTL interface levels.
15 MR/nOE Input Pulldown
internal dividers are reset and the outputs are in high impedance (HI-Z). When logic LOW, the internal dividers and the outputs are enabled. See Table 3E. LVCMOS/LVTTL interface levels. 17 V DDO_B Power Output supply pin for QBx outputs. 18, 19, 20 QB2, QB1, QB0 Output Single-ended Bank QB x clock outputs. LVCMOS/ LVTTL interface levels. 22 V DDO_AA Power Output supply pin for QAA output. 23 QAA Output Single-ended QAA clock outpu t. LVCMOS/LVTTL interface levels. 25 V DDO_AB Power Output supply pin for QAB output. 26 QAB Output Single-ended QAB clock outpu t. LVCMOS/LVTTL interface levels. 28 F_SELAA0 Input Pullup Frequency select pin for QAA output. See Table 3A. LVCMOS/LVTTL interface levels. F_SELAA2 Input Pulldown Frequency select pins for QAA output. See Table 3A. LVCMOS/LVTTL interface levels. 30, 31 SLEW0, SLEW1 Input Pulldown Slew rate select pins for LVCMOS/LVTTL clock output. LVCMOS/LVTTL interface levels.
Table 2. Pin Characteristics NOTE: Using 25MHz reference.
4©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Table 3C. Bank QB Frequency Select Function Table NOTE: Using 25MHz reference. Table 3D. REF_SEL Function Table Table 3E. MR/nOE Function Table NOTE: The device requires a reset signal after power-up to function properly. Table 3F. nOE_REF Function Table Inputs Output Frequencies F_SELB2 F_SELB1 F_SELB0 NB Divi der Value QB[0:2] (MHz) L L L 60 33.33 (default) LLH 4 0 5 0 L H L 30 66.67 L H H 24 83.33 H L L 20 100 H L H 16 125 H H L 15 133.33 H H H 12 166.67 Input REF_SEL Input Reference 0 (default) XTAL_IN 1R E F _ I N Input MR/nOE Function 0 (default) Output Enabled
1 Device reset, outputs disabled (LOW)
nOE_REF Function
0 REF_OUT [1:0] enabled
1 (default) REF_OUT [1:0] disabled (LOW)
5©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_REF = VDDO_AA = VDDO_AB = VDDO_B = 3.3V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_AA, VDDO_AB, VDDO_B, VDDO_REF. NOTE: IDDO_X denotes IDDO_AA + IDDO_AB + IDDO_B + IDDO_REF. Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_REF = VDDO_AA = VDDO_AB = VDDO_B = 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_AA, VDDO_AB, VDDO_B, VDDO_REF. NOTE: IDDO_X denotes IDDO_AA + IDDO_AB + IDDO_B + IDDO_REF. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 36.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.23 3.3 V DD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current SLEW[1:0] = 11, QAA = QB[0:2] = 166.67MHz, QAB = 125MHz, REF_OUT[0:1] = 25MHz, Outputs Not Loaded 180 mA IDDA Analog Supply Current 23 mA IDDO_X Output Supply Current 71 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.23 3.3 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current SLEW[1:0] = 11, QAA = QB[0:2] = 166.67MHz, QAB = 125MHz, REF_OUT[0:1] = 25MHz, Outputs Not Loaded 180 mA IDDA Analog Supply Current 23 mA IDDO_X Output Supply Current 21 mA
NOTE: VDDO_X denotes VDDO_AA, VDDO_AB, VDDO_B, VDDO_REF. NOTE 1: Outputs terminated with 50 to VDDO_X/2. See Parameter Measurement Information Section, Load Test Circuit diagrams. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
7©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Table 6A. AC Characteristics, VDD = VDDO_REF = VDDO_AA = VDDO_AB = VDDO_B = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_X/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: Jitter performance using XTAL inputs. NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency QAB 125 MHz QAA, QB[0:2] 33.33 166.67 MHz tsk(o) Output Skew; NOTE 1, 2 f OUT = 125MHz; SLEW[1:0] = 00 485 ps tsk(b) Bank Skew; NOTE 2, 3 QB[0:2] f OUT = 125MHz; SLEW[1:0] = 00 110 ps tjit(per) Period Jitter, RMS; NOTE 4 f OUT = 125MHz; SLEW[1:0] = 00 7 ps tjit(cc) Cycle-to-Cycl e Jitter; NOTE 2 f OUT = 125MHz; SLEW[1:0] = 00 90 ps tSLEW Slew Rate, Single-ended Output Clock; NOTE 5 QAA SLEW[1:0] = 00, Rise/Fall Time: 20% to 80% 1.93 3.0 V/ns QAB 2.84 4.75 V/ns QAA SLEW[1:0] = 01, Rise/Fall Time: 20% to 80% 1.76 2.75 V/ns QAB 2.45 4.25 V/ns QAA SLEW[1:0] = 10, Rise/Fall Time: 20% to 80% 1.58 2.50 V/ns QAB 1.88 3.0 V/ns QAA SLEW[1:0] = 11, Rise/Fall Time: 20% to 80% 0.98 1.65 V/ns QAB 1.03 1.75 V/ns t LOCK PLL Lock Time SLEW[1:0] = 00 20 ms odc Output Duty Cycle fOUT 125MHz; SLEW[1:0] = 00 47 53 % fOUT > 125MHz; SLEW[1:0] = 00 45 55 %
8©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO_REF = VDDO_AA = VDDO_AB = VDDO_B = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO_X/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: Jitter performance using XTAL inputs. NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency QAB 125 MHz QAA, QB[0:2] 33.33 166.67 MHz tsk(o) Output Skew; NOTE 1, 2 f OUT = 125MHz; SLEW[1:0] = 00 435 ps tsk(b) Bank Skew; NOTE 2, 3 QB[0:2] f OUT = 125MHz; SLEW[1:0] = 00 115 ps tjit(per) Period Jitter, RMS; NOTE 4 f OUT = 125MHz; SLEW[1:0] = 00 12 ps tjit(cc) Cycle-to-Cycl e Jitter; NOTE 2 f OUT = 125MHz; SLEW[1:0] = 00 96 ps tSLEW Slew Rate, Single-ended Output Clocks; NOTE 5 QAA SLEW[1:0] = 00, Rise/Fall Time: 20% to 80% 1.36 2.15 V/ns QAB 1.89 3.25 V/ns QAA SLEW[1:0] = 01, Rise/Fall Time: 20% to 80% 1.12 1.85 V/ns QAB 1.43 2.50 V/ns QAA SLEW[1:0] = 10, Rise/Fall Time: 20% to 80% 0.88 1.55 V/ns QAB 1.06 1.85 V/ns QAA SLEW[1:0] = 11, Rise/Fall Time: 20% to 80% 0.59 1.15 V/ns QAB 0.66 1.15 V/ns t LOCK PLL Lock Time SLEW[1:0] = 00 25 ms odc Output Duty Cycle fOUT 125MHz; SLEW[1:0] = 00 45 55 % fOUT > 125MHz; SLEW[1:0] = 00 43 57 %
9©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Output Skew RMS Period Jitter 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit Bank Skew Output Slew Rate SCOPE Qx GND 1.65V±5% -1.65V±5% VDDA 1.65V±5% VDD, VDDO_AA, VDDO_AB, VDDO_B, VDDO_REF tsk(o) VDDO VDDO Qx Qy VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram SCOPE Qx GND VDD 1.25V±5% -1.25V±5% 2.05V±5% VDDA 2.05V±5% VDDO_AA, VDDO_AB, VDDO_B, VDDO_REF tsk(b) VDDOX VDDOX QB[0:2] QB[0:2] 20% 80% 80% 20% tR tF VFVR tSLEW = VR/tR QAA, QAB, QB[0:2]
10©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Parameter Measurement Information, continued Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_IN Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. ➤➤ ➤➤ VDDOX VDDOX VDDOX tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
QAA, QAB, QB[0:2] tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QAA, QAB, QB[0:2], REF_OUT[0:1]
14©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 840S07I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 840S07I is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum current at 85°C is as follows: IDD_MAX = 168.5mA IDDA_MAX = 20.96mA IDDO_MAX = 74.11mA Core Output Power Dissipation Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(168.5mA + 20.96mA) = 656.51mW Power (output) MAX = VDDO_MAX * IDDO = 3.465V *74.11mA = 256.80mW LVCMOS Output Power Dissipation Output Impedance R OUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 35)] = 20.38mA Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 35 * (20.38mA)2 = 14.54mW per output Total Power Dissipation on the R OUT Total Power (ROUT) = 14.54mW * 7 = 101.8mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output Total Power (25MHz) = 3mW * 2 = 6mW Dynamic Power Dissipation at 166.67MHz Power (166.67MHz) = CPD * Frequency * (VDDO)2 = 10pF * 166.67MHz * (3.465V)2 = 20mW per output Total Power (166.67MHz) = 20mW * 5 = 100.1mW Total Power Dissipation Total Power = Power (core) + Power (output) + Total Power (25MHz + Total Power (166.67MHz) = 1121.15mW
wire and bond pad temperature remains below 125°C. flow of 1 meter per second and a multi-layer board, the appropriate value is 30.6°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead TQFP, E-Pad, Forced Convection
Table 8. JA vs. Air Flow Table for a 32 Lead TQFP, E-Pad
Table 9. Package Dimensions 32 Lead TQFP, E-Pad
0.20 TAB
18©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet
Ordering Information
Table 9. Ordering Information
19©2016 Integrated Device Technology, Inc Revision A April 14, 2016 840S07I Data Sheet
Revision History
Revision Date Description of Change April 14, 2016 ▪ Removed ICS from part number where needed. ▪ Ordering Information - removed quantity from tape and reel. Deleted LF note below table. ▪ Updated data sheet header and footer.
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