840S06AKILF

ICS840S06I IDT | Alldatasheet

Document overview

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Technical content

Features

• Six LVCMOS/ LVTTL outputs, 20Ω typical output impedance - One selectable core clock for the processor - One selectable clock for the PCI/ PCI-X bus - One 125MHz clock reference for GbE MAC - Three 25MHz clock references for GbE PHY
• Selectable external crystal or differential (single-ended) input source
• Crystal oscillator interface designed for 25MHz, parallel resonant crystal
• Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL input levels
• Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
• Full 3.3V or mixed 3.3V core/2.5V output supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages HiPerClockS™ ICS Pin Assignment 91 0 1 1 12 13 14 15 16 32 31 30 29 28 27 26 25 VDD nPLL_SEL XTAL_IN XTAL_OUT nXTAL_SEL CLK nCLK GND QB GND GND nc VDDO_A VDDO_B nOE_REF CORE_SEL nc nc VDDA PCI_SEL0 PCI_SEL1 VDDO_REF QREF0 QREF1 QREF2 GND QC VDDO_C ICS8430S07I 32-Lead VFQFN 5mm x 5mm x 0.75mm package body K Package Top View VDD QA VDDO_REF ICS840S06I 32-Lead VFQFN 5mm x 5mm x 0.75mm Package body K Package Top View nc The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 2 ICS840S06AKI REV. AI JULY 10, 2008 Block Diagram

25 MHz CLK

nPLL_SEL

25 MHz

XTAL_IN XTAL_OUT 0 = 50.000 MHz 1 = 33.333 MHz Processor Core Clock (LVCMOS)

125 MHz GbE CLK

25 MHz GbE CLK

00 = 133.333 MHz 01 = 100.000 MHz 10 = 66.667 MHz 11 = 33.333 MHz PCI or PCI-X Clock (LVCMOS) Gigabit Ethernet MAC Clock (LVCMOS) \\ Gigabit Ethernet / PHY Clocks / (LVCMOS) nXTAL_SEL QA QB QC QREF0 QREF1 QREF2 CORE_SEL PCI_SEL1:0 Clock Output Control Logic nOE_REF

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 15 V DD Power Core supply pins. the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. XTAL_OUT Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. input when HIGH. LVCMOS/LVTTL interface levels. 6 CLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. Internal resistor bias to VDD/2. 8, 20, 21, 27 GND Power Power supply ground. PCI_SEL0 Input Pulldown Selects the PCI/PCI-X reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. 11, 12, 13, 14 nc Unused No connect. 16 V DDA Power Analog supply pin. 17 V DDO_A Power Bank A output supply pin. 3.3 V or 2.5V supply. Output Single-ended outputs. LVCM OS/LVTTL interface levels.

22 CORE_SEL Input Pulldown

50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. 24 V DDO_B Power Bank B output supply pin. 3.3 V or 2.5V supply. 25 V DDO_C Power Bank C output supply pin. 3.3 V or 2.5V supply. 28, 32 V DDO_REF Power REF bank output supply pins. 3.3 V or 2.5V supply.

Table 2. Pin Characteristics NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF .

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 5 ICS840S06AKI REV. AI JULY 10, 2008 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF . Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes VDDO_B, VDDO_C, VDDO_D and VDDO_REF . Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO (LVCMOS) -0.5V to V DD + 0.5V Outputs, IO (LVPECL) Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, θ JA 39.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.16 3.3 V DD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 140 mA IDDA Analog Supply Current 16 mA IDDO_X Output Supply Current 20 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.16 3.3 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 130 mA IDDA Analog Supply Current 16 mA IDDO_X Output Supply Current 16 mA

NOTE 1: Outputs terminated with 50Ω to VDDO_X/2. See Parameter Measurement Information, Output Load Test Circuit diagram. NOTE 1: VIL should not be less than -0.3V. NOTE 2. Common mode voltage is defined as VIH. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.

Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Refer to the phase noise plot. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 8 ICS840S06AKI REV. AI JULY 10, 2008 Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Differential Input Level RMS Phase Jitter 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit LVCMOS Part-to-Part Skew Output Rise/Fall Time SCOPE Qx LVCMOS GND -1.65V±5% VDDO_X 1.65V±5% VDD, VDDA 1.65V±5% nCLK CLK VDD GND V CMR Cross Points V PP Phase Noise Mask Offset Frequencyf1 f2 Phase Noise Plot RMS Jitter = Area Under the Masked Phase Noise Plot Noise Power SCOPE Qx GND LVCMOS -1.25V±5% VDDO_X 2.05V±5% 1.25V±5% VDD VDDA 2.05V±5% tsk(pp) VDDOX VDDOX Part 1 Part 2 Qx Qy 20% 80% 80% 20% tR tF QA:QC, QREF[0:2]

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 9 ICS840S06AKI REV. AI JULY 10, 2008 Parameter Measurement Information, continued Bank Skew Output Duty Cycle/Pulse Width/Period Cycle-to-Cycle Jitter tsk(b) VDDOX VDDOX QREF[0:2] QREF[0:2] tPERIOD tPW tPERIOD odc = VDDOX x 100% tPW QA:QC, QREF[0:2] ➤➤ ➤➤ VDDOX VDDOX VDDOX tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA:QC, QREF[0:2]

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 11 ICS840S06AKI REV. AI JULY 10, 2008 Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating We recommend that there is no trace attached.

the package to maximize the thermal/electrical performance. for the leads to avoid any shorts. Enhance Leadfame Base Package, Amkor Technology. Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 15 ICS840S06AKI REV. AI JULY 10, 2008 Power Considerations This section provides information on power dissipation and junction temperature for the ICS840S06I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS840S06I is the sum of the core power, analog power, and power dissipated in the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core Output Power Dissipation  Power (core) _MAX = VDD_MAX * (IEE_MAX + IDDA + IDDO) = 3.465V * (140mA + 16mA + 20mA) = 609.84mW LVCMOS Output Power Dissipation  Output Impedance R OUT Power Dissipation due to Loading 50Ω to VDDO/2 Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.8mA  Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.8mA)2 = 12.3mW per output  Total Power Dissipation on the R OUT Total Power (ROUT) = 12.3mW * 6 = 73.8mW  Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW  Dynamic Power Dissipation at 133MHz Power (133MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133MHz * (3.465V)2 = 16mW per output Total Power (133MHz) = 16mW * 3 = 48mW Total Power Dissipation  Total Power = Power (core) + Total Power (ROUT) + Total Power (25MHz) + Total Power (133MHz) = 610mW + 73.8mW + 9mW + 48mW = 741mW

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below. of board (single layer or multi-layer). Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.

dimensions are in Table 9 below. Table 9. Package Dimensions

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY IDT™ / ICS™ CLOCK GENERATOR 19 ICS840S06AKI REV. AI JULY 10, 2008

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.

CLOCK GENERATOR FOR CAVIUM PROCESSORS PRELIMINARY www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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