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Technical content
Features
- Four single-ended LVCMOS/LVTTL clock outputs
- One REF_OUT LVCMOS/LVTTL clock output
- Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference input
- Supports the following output frequencies on either bank: 33.33MHz, 50MHz, 66.67MHz, 83.33MHz, 100MHz, 125MHz, 133.33MHz, and 166.67MHz
- VCO: 2GHz
- Slew rate control
- Output supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V
- -40°C to 85°C ambient operating temperature
- Lead-free (RoHS 6) packaging 840S05I 32-Lead TQFP, E-Pad 7mm x 7mm x 1mm package body Y Package Top View Pin AssignmentBlock Diagram PLL VCO 2GHz M = ÷80 ÷NA ÷NB OSC QA0 QA1 QB0 QB1 REF_OUT SLEW[1:0] REF_IN REF_SEL XTAL_IN XTAL_OUT 25MHz Pulldown MR/nOE Pulldown Pulldown Pulldown Pulldown Pulldown Pullup nREF_OE F_SELB[2:0] F_SELA[0, 2] F_SELA1 Pullup VDDA VDD XTAL_OUT XTAL_IN GND REF_SEL REF_IN F_SELB2 GND QA0 QA1 VDDO_A GND QB0 QB1 VDDO_B nREF_OE VDDO_REF REF_OUT nc GND F_SELB1 MR/nOE F_SELB0 SLEW1 SLEW0 F_SELA1 F_SELA0 GND nc V DD F_SELA2 9 12345678 24 23 22 21 20 19 18 17 840S05I Data Sheet Crystal-to-LVCMOS/LVTTL Frequency Synthesizer
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1V DDA Power Analog supply pin. 2, 25 V DD Power Core supply pin. XTAL_IN Input Crystal oscillator inte rface. XTAL_IN is the input. XTAL_OUT is the output. 20, 24, 27 GND Power Power supply ground. 6 REF_SEL Input Pulldown Reference select pin. Se e Table 3C. LVCMOS/LVTTL interface levels. 7 REF_IN Input Pulldown Single-ended 25MHz reference clock input. LVCMOS/LVTTL interface levels. Input Pulldown Frequency select pins for Bank B outputs. See Table 3A. LVCMOS/LVTTL interface levels. 9 nREF_OE Input Pullup Active low REF_OUT enable/disable pin. See Table 3D. LVCMOS/LVTTL interface levels. 10 V DDO_REF Power Output supply pin for REF_OUT clock output. 11 REF_OUT Output Single-ended LVCMOS/LVTTL reference clock output. 12, 26 nc Unused No connect. 15 MR/nOE Input Pulldown Active HIGH Master Reset. Active LOW output enable. See Table 3E. LVCMOS/LVTTL interface levels. 17 V DDO_B Power Output supply pin for QBx outputs. 18, 19 QB1, QB0 Output Single-ended Bank B clo ck outputs. LVCMOS/LVTTL interface levels. 21 V DDO_A Power Output supply pin for QAx outputs. 22, 23 QA1, QA0 Output Single-ended Bank A clo ck outputs. LVCMOS/LVTTL interface levels. F_SELA2 Input Pullup Frequency select pins for Bank A outputs. See Table 3A. LVCMOS/LVTTL interface levels. 29 F_SELA1 Input Pulldown Frequency select pin for Bank A outputs. See Table 3A. LVCMOS/LVTTL interface levels. SLEW1 Input Pulldown Slew rate select pins for LVCMOS/LVTTL clock output. See Table 3B. LVCMOS/LVTTL interface levels.
Table 2. Pin Characteristics NOTE 1: Characterized with SLEW[1:0] = 00. NOTE: Using 25MHz reference.
4©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Table 3B. Slew Rate Function Table NOTE: Typical values for VDDO_A, VDDO_B = 3.3V. Refer to the AC Characteristics Table for more details. Table 3C. REF_SEL Function Table Table 3D. nREF_OE Function Table Table 3E. MR/nOE Function Table NOTE: A MR/OE pulse is required after device power-up to guarantee functionality. Setting Slew Rate (v/ns)SLEW1 SLEW0 0 0 3.5 (Default) 01 2 . 6 10 1 . 8 11 1 . 0 REF_SEL Input Reference 0 (Default) XTAL_IN 1R E F _ I N nREF_OE REF_OUT State
0 REF_OUT enabled
1 (Default) REF_OUT disabled (Logic LOW) MR/nOE Function 0 (Default) QA and QB outputs enabled. 1 Device reset, QA and QB outputs disabled (Logic LOW).
5©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO_REF = VDDO_A = VDDO_B = 3.3V ± 5%, TA = -40°C to 85°C NOTE: All parameters specified for inputs and outputs under static conditions, unless otherwise noted. Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_REF = VDDO_A = VDDO_B = 2.5V ± 5%, TA = -40°C to 85°C NOTE: All parameters specified for inputs and outputs under static conditions, unless otherwise noted. Item Rating Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 36.2C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDO_A, VDDO_B, VDDO_REF Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 160 mA IDDA Analog Supply Current 20 mA IDDO_A, IDDO_B Output Supply Current SLEW[1:0] = 11, QA[1:0], QB[1:0] = 166.67MHz; REF_OUT = 25MHz, Outputs Not Loaded 30 mA IDDO_REF Output Supply Current Outputs Not Loaded 2 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDO_A, VDDO_B, VDDO_REF Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 160 mA IDDA Analog Supply Current 20 mA IDDO_A, IDDO_B Output Supply Current SLEW[1:0] = 11, QA[1:0], QB[1:0] = 166.67MHz; REF_OUT = 25MHz, Outputs Not Loaded 10 mA IDDO_REF Output Supply Current Outputs Not Loaded 1 mA
NOTE: VDDO_X denotes VDDO_A, VDDO_B, VDDO_REF. NOTE 1: Outputs terminated with 50 to VDDO_A, _B, _REF/2. See Parameter Measurement Information, Output Load Test Circuit diagram. NOTE 2: Characterized with QA[1:0], QB[1:0] = 33.33MHz and REF_OUT = 25MHz. Table 5. Crystal Characteristics NOTE: Characterized using an 18pF parallel resonant crystal.
7©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Table 6A. AC Characteristics, VDD = VDDO_REF = VDDO_A = VDDO_B = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO_A, _B, _REF/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: Characterized using a 25MHz Crystal input. REF_OUT is disabled. NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency QA[1:0] 33.33 166.67 MHz QB[1:0] 33.33 166.67 MHz tsk(o) Output Skew; NOTE 1, 2 QA[1:0] or QB[1:0] fOUT 125MHz, 25MHz Crystal Input 180 ps tsk(b) Bank Skew; NOTE 2, 3 QA[1:0] or QB[1:0] SLEW[1:0] = 00 35 ps tjit(per) Period Jitter, RMS; NOTE 4 fOUT = 125MHz, SLEW[1:0] = 00 3.4 ps fOUT = 125MHz, SLEW[1:0] = 01 3.4 ps fOUT = 125MHz, SLEW[1:0] = 10 3.5 ps fOUT = 125MHz, SLEW[1:0] = 11 4.6 ps tSLEW Slew Rate; NOTE 5 QA[1:0] or QB[1:0] SLEW[1:0] = 00, Rise/Fall Time: 20% to 80% 3.5 5.0 V/ns QA[1:0] or QB[1:0] SLEW[1:0] = 01, Rise/Fall Time: 20% to 80% 2.6 3.8 V/ns QA[1:0] or QB[1:0] SLEW[1:0] = 10, Rise/Fall Time: 20% to 80% 1.8 2.7 V/ns QA[1:0] or QB[1:0] SLEW[1:0] = 11, Rise/Fall Time: 20% to 80% 1.0 1.7 V/ns tL PLL Lock Time SLEW[1:0] = 00 20 ms odc Output Duty Cycle QA[1:0] or QB[1:0] 25MHz Crystal Input, SLEW[1:0] = 00 45 55 %
8©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Table 6B. AC Characteristics, VDD = 3.3V ± 5%, VDDO_REF = VDDO_A = VDDO_B = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO_A, _B, _REF/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: Characterized using a 25MHz Crystal input. REF_OUT is disabled. NOTE 5: A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency QA[1:0] 33.33 166.67 MHz QB[1:0] 33.33 166.67 MHz tsk(o) Output Skew; NOTE 1, 2 QA[1:0] or QB[1:0] fOUT 125MHz, 25MHz Crystal Input 210 ps tsk(b) Bank Skew; NOTE 2, 3 QA[1:0] or QB[1:0] SLEW[1:0] = 00 45 ps tjit(per) Period Jitter, RMS; NOTE 4 fOUT = 125MHz, SLEW[1:0] = 00 3.5 ps fOUT = 125MHz, SLEW[1:0] = 01 3.6 ps fOUT = 125MHz, SLEW[1:0] = 10 4.1 ps fOUT = 125MHz, SLEW[1:0] = 11 6.3 ps tSLEW Slew Rate; NOTE 5 QA[1:0] or QB[1:0] SLEW[1:0] = 00, Rise/Fall Time: 20% to 80% 3.0 4.5 V/ns QA[1:0] or QB[1:0] SLEW[1:0] = 01, Rise/Fall Time: 20% to 80% 2.2 3.4 V/ns QA[1:0] or QB[1:0] SLEW[1:0] = 10, Rise/Fall Time: 20% to 80% 1.6 2.6 V/ns QA[1:0] or QB[1:0] SLEW[1:0] = 11, Rise/Fall Time: 20% to 80% 0.9 1.7 V/ns tL PLL Lock Time SLEW[1:0] = 00 25 ms odc Output Duty Cycle QA[1:0] or QB[1:0] 25MHz Crystal Input, SLEW[1:0] = 00 45 55 %
9©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit Output Skew RMS Period Jitter 3.3V Core/2.5V LVCMOS Output Load Test Circuit Bank Skew Output Slew Rate SCOPE Qx GND 1.65V±5% -1.65V±5% VDDA 1.65V±5% VDD, VDDO_A, VDDO_B, VDDO_REF ts k(o) VDDO_X VDDO_Y Qx Qy VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram SCOPE Qx GND VDD 1.25V±5% -1.25V±5% 2.05V±5% VDDA 2.05V±5% VDDO_A, VDDO_B, VDDO_REF t sk(b) VDDO_X VDDO_X QX0 QX1 Where X is either Bank A or Bank B 20% 80% 80% 20% tR tF VFVR tSLEW = VR/tR QA[1:0], QB[1:0]
10©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_IN Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_IN to ground. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. There should be no trace attached. tPERIOD tPW tPERIOD odc = VDDO_X x 100% tPW QA[1:0], QB[1:0]
and the inner edges of pad pattern for the leads to avoid any shorts. Enhance Leadframe Base Package, Amkor Technology. Figure 2. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
13©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Schematic Layout Figure 3 shows an example 840S05I application schematic. This schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In this schematic, the device is operated at VDD=VDDA = 3.3V and VDDO_A, VDDO_B and VDDO_REF=2.5V. An 18pF parallel resonant 25MHz crystal is used with the recommended load capacitors C1 = 33pF and C2 = 27pF for frequency accuracy. Depending on the parasitic capacity on the crystal terminals of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 840S05I provides separate power supply pins to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µf capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
Figure 3. 840S05I Application Schematic
15©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 840S05I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 840S05I is the sum of the core power plus the analog power plus the power dissipation in the load(s). The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results. The maximum current at 85°C is as follows: IDD_MAX = 160mA IDDA_MAX = 20mA Core Power Dissipation
- Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(160mA + 20mA) = 623.7mW LVCMOS Output Power Dissipation
- Output Impedance R OUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 22)] = 24.06mA
- Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 22 * (24.06mA)2 = 12.74mW per output
- Total Power Dissipation on the R OUT Total Power (ROUT) = 12.74mW * 5 = 63.7mW
- Dynamic Power Dissipation at 25MHz (REF_OUT) Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.2mW per output Total Power (25MHz) = 1.2mW * 1 = 1.2mW
- Dynamic Power Dissipation at 166.67MHz (QA[1:0], QB[1:0]) Power (166.67MHz) = CPD * Frequency * (VDDO)2 = 16pF * 166.67MHz * (3.465V)2 = 32.02mW per output Total Power (166.67MHz) = 32.02mW * 4 = 128.08mW Total Power Dissipation
- Total Power = Power (core) + Power (output) + Total Power (25MHz) + Total Power (166.67MHz) = 623.7mW + 63.7mW + 1.2mW + 128.08mW = 816.68mW
wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 36.2°C/W per Table 7 below. Table 7. Thermal Resistance JA for 32 Lead TQFP , E-Pad, Forced Convection
Table 8. JA vs. Air Flow Table for a 32 Lead TQFP, E-Pad
Table 9. Package Dimensions 32 Lead TQFP , E-Pad
0.20 TAB
19©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet
Ordering Information
Table 10. Ordering Information
20©2016 Integrated Device Technology, Inc Revision A April 11, 2016 840S05I Data Sheet
Revision History
Revision Date Description of Change April 11, 2016 ▪ Removed ICS from part number where needed. ▪ Updated data sheet header and footer.
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