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Technical content

Features

  • Ten LVCMOS clock outputs: four system clocks, four DDR clocks, one RTC output, and one 25MHz reference clock
  • Selectable input reference: crystal oscillator interface or differential LVPECL input
  • Output Frequency Range: 25MHz - 200MHz
  • Serial Interface: I2C programmable
  • Frequency Margining in <0.312MHz steps
  • Spread spectrum for EMI reduction
  • VCO range: 2GHz – 2.4GHz
  • Voltage supply modes: Core (VDD, VDDXTAL, VDDA) all core voltages must be identical Output (VDDO_A,VDDO_B, VDDO_C, VDDO_REF0, VDDO_REF1) Core / Output 3.3V / 3.3V 3.3V / 2.5V 3.3V / 1.8V 2.5V / 2.5V 2.5V / 1.8V
  • Output voltage levels are independently selectable
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging Pin Assignment XTAL (MHz) FSEL[3:0] SYSCLK QA & QB (MHz) DDRCLK QC (MHz) 25 0000 66.67 66.67 25 0001 66.67 100 25 0010 66.67 125 25 0011 66.67 133.33 25 0100 100 66.67 25 0101 100 100 25 0110 100 125 25 0111 100 133.33 25 1000 125 66.67 25 1001 125 100 25 1010 125 125 25 1011 125 133.33 25 1100 133.33 66.67 25 1101 133.33 100 25 1110 133.33 125 25 1111 133.33 133.33 XTAL_OUT XTAL_IN VDDXTAL PCLK nPCLK VDD GND_REF OE_REF QREF0 VDDO_REF0 VDDO_REF1 QREF1 SSC_EN SADR SDATA SCLK V DD GND_QC QC3 QC2 QC1 QC0 V DDO_C VDDO_C GND_QA REFOUT_SEL OE_B OE_A QA VDDO_A VDDO_B QB0 QB1 QB2 GND_QB OE_C REF_SEL GND_XTAL PLL_SEL MR VDD GND VDDA GNDA FSEL0 FSEL2 FSEL1 FSEL3 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 302 92 8 27 26 25 840NT4 840NT4 48-lead, 7.0mm x 7.0mm VFQFN

REVISION 1 6/16/14 2 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Block Diagram QA XTAL1_IN XTAL1_OUT REF_SEL Pulldown PullupPLL_SEL IC C o n t r o l (Frequency, Spread-Spectrum Clocking) SCLK SDATA Pulldown FSEL[3:0] SSC_EN Pulldown Pulldown Phase Detector PCLK nPCLK Pullup/ Pulldown QB1 QB2 VCO ÷M÷M ÷N1 Configuration Interface Logic (Frequency) MR OE_B OE_A Pullup Pullup VDDO_B Pulldown OSC VDD VDDA QB0 OE_REF VDDO_A QREF0 VDDO_REF0 ÷N2 QC0 VDDO_C Pullup OE_C QREF1 0= ÷8 1= ÷16 REFOUT_SEL Pulldown (DDR Clocks) (System Clocks) (RTC) VDDO_REF1 SADR QC1 QC2 QC3 Pulldown Pullup

Table 1. Pin Descriptions XTAL_OUT Input Crystal oscillator interface. XTAL _IN is the input, XTAL_OUT is the output. 6, 32, 44 V DD Power Core supply pins. 3V DDXTAL Power Power supply pin for crystal oscillator. 4 PCLK Input Pulldown Non-inverting external 25MHz differential LVPECL reference input. 7 GND_REF Power Power supply ground for QREF clock outputs. high-impedance mode on disable. LVCMOS/LVTTL interface levels. 9 QREF0 Output Single-ended RTC clock output. LVCMOS/LVTTL interface levels. Power Output power supply for QREF0 and QREF1 outputs. 12 QREF1 Output Single-ended reference clo ck output. LVCMOS/LVTTL interface levels. 13 REFOUT_SEL Input Pulldown Selects the real-time clock output frequency as defined in Table 3B. LVCMOS/LVTTL interface levels. 14 GND_QA Power Power supply ground for QA outputs. high-impedance mode on disable. LVCMOS/LVTTL interface levels. high-impedance mode on disable. LVCMOS/LVTTL interface levels. 17 QA Output Single-ended system clock output. LVCMOS interface levels. 18 V DDO_A Power Output power supply for QA clock output. 19 VDDO_B Power Output power supply for Bank QBx clock outputs. 20, 21, 22 QB0, QB1, QB2 Output Single-ended system clock output s. LVCMOS/ LVTLL interface levels. 23 GND_QB Power Power supply ground for QB outputs. high-impedance mode on disable. LVCMOS/LVTTL interface levels. 25, 30 V DDO_C Power Output power supply for Bank QCx outputs. QC2, QC3 Output Single-ended DDR clock outputs. LVCMOS/ LVTLL interface levels. 31 GND_QC Power Power supply ground for QC outputs. 33 SCLK Input I 2C clock input. LVCMOS/LVTTL interface levels. 34 SDATA Input I2C data input/ output. Input: LVCMOS/ LVTLL interface levels. 35 SSC_EN Input Pulldown SSC control pin. SSC is enabled when SSC_EN is HIGH. LOW disables SSC. See Table 3C. LVCMOS/LVTTL interface levels. 36 SADR Input Pulldown I 2C unique address select pin. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF0, VDDO_REF1. Selects the System and DDR clock output frequencies as defined in Table 3A. 41 GNDA Power Power supply ground for PLL analog. 42 V DDA Power Analog supply pin. 43 GND Power Power supply ground. affect REF_OUT. LVCMOS/LVTTL interface levels.

46 PLL_SEL Input Pullup

the PLL (PLL Bypass). When HIGH, selects the PLL (PLL enable). LVCMOS/LVTTL interface levels. 47 REF_SEL Input Pulldown Select input for XTAL (LOW) or PCLK, nPCLK (HIGH). LVCMOS/LVTTL interface levels. 48 GND_XTAL Power Power supply ground for XTAL.

REVISION 1 6/16/14 5 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Function Tables Table 3A. System & DDR Clock Output Frequency Select Table, FM_EN = "0" Table 3B. RTC Output Frequency Select Table Table 3C. SSC Control Settings NOTE: *SSC_EN = 1. Disables M divider programming when frequency margining is also enabled. N divider programming is still available. XTAL (MHz) FSEL[3:0] System Clocks (MHz) QA & QB[2:0] DDR Clocks (MHz) QC[3:0] 25 0000 (default) 66.67 66.67 25 0001 66.67 100 25 0010 66.67 125 25 0011 66.67 133.33 25 0100 100 66.67 25 0101 100 100 25 0110 100 125 25 0111 100 133.33 25 1000 125 66.67 25 1001 125 100 25 1010 125 125 25 1011 125 133.33 25 1100 133.33 66.67 25 1101 133.33 100 25 1110 133.33 125 25 1111 133.33 133.33 XTAL (MHz) REFOUT_SEL Output Di vider QREF0 (MHz) QREF1 (MHz) 25 0 (default) ÷8 3.125 25 25 1 ÷16 1.5625 25 XTAL (MHz) SSC_EN SSC Profile 25 0 (default) SSC Off 25 1 * Typical -0.5% down-spread, 30kHz – 32kHz, triangular waveform

REVISION 1 6/16/14 6 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Principles of Operation Output frequencies are synthesized from an external 25MHz LVPECL or crystal (fXTAL) input. The device contains a 11-bit PLL feedback divider (M) with a prescaler (P) and an 7-bit output divider (N). The output frequency f OUT is calculated using the following equation: or The M and N PLL-dividers have corresponding I2C registers. These registers can be directly programmed to allow for frequency margining. (See Tables 4E, 4F , 4G, & 4H). Each I2C configuration register has a default setting determined by the FSEL[3:0] strap pins. The default setting is automatically loaded into the registers (defined in Table 4D) at power up and with the release of MR. Frequency Margining The M and N registers are normally configured at power up by the state of the FSEL[3:0] pins. These registers can be overwritten by setting the FM_EN bit to a 1 and then directly writing desired values to the M and N registers. Frequency margining is only allowed with SSC disabled. Enabling SSC will block direct user programming of the M and N registers. See Tables 4F , 4G and 4H for M and N divider coding. Register Settings Table 4A. I2C Device Slave Address Table 4B. Block Write Operation Table 4C. Block Read Operation M fOUT = fXTAL · P · N M fOUT = PCLK · P · N

110000 S A D R R / W

R/W(0) ACK Register Byte Pointer (BP) ACK Data Byte (for Register BP) ACK Data Byte (for Register BP+1) ACK Data Byte (for Register BP+...) ACK STOP Length (bits) 1 7 1 181 8 1 8 1 8 1 1 Description START Slave Address Read Bit R/W(1) ACK Register Byte Pointer (BP) ACK Data Byte (for Register BP) ACK Data Byte (for Register BP+1) ACK Data Byte (for Register BP+...) ACK STOP Length (bits) 1 7 1 181 8 1 8 1 8 1 1

REVISION 1 6/16/14 7 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 4D. I2C Register Map NOTE: The QREF[0:1], QCx disable bits can be programmed at any time to override and disable the OE_REF and OE_QC per individual outputs. This can be done whether SSC_OFF frequency margining is enabled or disabled. If the OE_REF or OE_QC are set to disable their respective outputs, the I2C bits cannot enable their respective outputs. Table 4E. I2C Register Function Descriptions Table 4F. PLL Feedback (M) Divider Coding for frequency margin mode, FM_EN = "1" Register Byte Binary Register Address Power Up Default D[7:0] Register Bit B i n a r y D e c i m a l D 7 D 6D 5D 4D 3D 2D 1D 0 0 00000000 00011110 N1 = 30 Reserved N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] Reserved 1 00000001 00011110 N2 = 30 Reserved N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] Reserved 2 00000010 01010000 M = 640 3 00000011 00000000 M[2] M[1] M[0] FM_EN Reserved Reserved QREF1 Disabled QREF0 Disabled 4 00000100 00001011 11 QC3 Disabled QC2 Disabled QC1 Disabled QC0 Disabled Reserved Reserved Reserved Reserved Bits Name Function M[10:0] Integer Feedback Divider Register Sets the feedback divider value. Can be set to a value of 4 to 1023. The minimum feedback value is 4. Programming 0x04 would yield a feedback divider of ÷4, 0x05 = ÷5, etc. It should also be noted that with a reference of 25MHz and internally fixed Pre-divider of 8, the values loaded into this register should be between 640 and 768 inclusively in order to remain at or above the minimum VCO frequency of 2.0GHz and at or below the maximum VCO frequency of 2.4GHz. N1[7:0] Output Divider Register Sets the output divider for output banks A and B. See Tables 4G and 4H for the output divider coding. N2[7:0] Output Divider Register Sets the output divider for output bank C. See Table 4G and 4H for the output divider coding. FM_EN Frequency Margin Enable Bit This bit must be set to “1” in order to enable frequency margining using Bytes [3:0]. Spread spectrum must also be OFF in order to use frequency margining. Register Bit M[10:0] Binary Decimal 01100000000 768 01011111111 767 01011111110 766 01010000010 642 01010000001 641 01010000000 640

REVISION 1 6/16/14 8 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 4G. PLL Feedback (M) and Output (N) Divider Coding for frequency margin mode, FM_EN = "1" NOTE: x = 1 or 2. NOTE: Nx Divider can only be even numbers 10 through 126. NOTE: M and Nx dividers can be programmed to achieve granularity of 0.312MHz or finer. XTAL or PCLK (MHz) Pre-scaler (P) Register Bit M Divider Nx Divider fVCO (MHz) f OUT (MHz)M[10:0] Nx[6:0] 25 8 01100000000 0001100 768 12 2400 200.00 25 8 01010000000 0001100 640 12 2000 166.67 25 8 01100000000 0001110 768 14 2400 171.43 25 8 01010000000 0001110 640 14 2000 142.86 25 8 01100000000 0010000 768 16 2400 150.00 25 8 01010000000 0010000 640 16 2000 125.00 25 8 01100000000 0010010 768 18 2400 133.33 25 8 01010000000 0010010 640 18 2000 111.11 25 8 01100000000 0010100 768 20 2400 120.00 25 8 01010000000 0010100 640 20 2000 100.00 25 8 01100000000 0011000 768 24 2400 100.00 25 8 01010000000 0011000 640 24 2000 83.33 25 8 01100000000 0011100 768 28 2400 85.71 25 8 01010000000 0011100 640 28 2000 71.43 25 8 01100000000 0100000 768 32 2400 75.00 25 8 01010000000 0100000 640 32 2000 62.50 25 8 01100000000 0100110 768 38 2400 63.16 25 8 01010000000 0100110 640 38 2000 52.63 25 8 01100000000 0101100 768 44 2400 54.55 25 8 01010000000 0101100 640 44 2000 45.45 25 8 01100000000 0110100 768 52 2400 46.15 25 8 01010000000 0110100 640 52 2000 38.46 25 8 01100000000 0111110 768 62 2400 38.71 25 8 01010000000 0111110 640 62 2000 32.26 25 8 01100000000 1001000 768 72 2400 33.33 25 8 01010000000 1001000 640 72 2000 27.78 25 8 01100000000 1010000 768 80 2400 30.00 25 8 01010000000 1010000 640 80 2000 25.00

REVISION 1 6/16/14 9 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 4H. PLL Output Divider (N) Coding for frequency margin mode, FM_EN = "1" NOTE: x = 1 or 2. NOTE: Nx Divider can only be even numbers 10 through 126. NOTE: M and Nx dividers can be programmed to achieve granularity of 0.312MHz or finer. Register Bit Nx Divider Output Frequency Range Nx[6:0] f OUT,MIN (MHz) f OUT,MAX (MHz) 0001100 12 166.67 200.00 0001110 14 142.86 171.43 0010000 16 125.00 150.00 0010010 18 111.11 133.33 0010100 20 100.00 120.00 0011000 24 83.33 100.00 0011100 28 71.43 85.71 0100000 32 62.50 75.00 0100110 38 52.63 63.16 0101100 44 45.45 54.55 0110100 52 38.46 46.15 0111110 62 32.26 38.71 1001000 72 27.78 33.33 1010000 80 25.00 30.00

REVISION 1 6/16/14 10 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF0,VDDO_REF1. Table 5A. Power Supply DC Characteristics, VDD = VDDXTAL = 3.3V ± 5%, VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF0,VDDO_REF1. NOTE: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF0 + IDDO_REF1. Table 5B. Power Supply DC Characteristics, VDD = VDDXTAL = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF0,VDDO_REF1. NOTE: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF0 + IDDO_REF1. Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO_X + 0.5V Junction Temperature, TJ 125C Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDXTAL XTAL Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.064 3.3 V DD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 136 14 9 mA IDDXTAL XTAL Power Supply Current 40 44 mA IDDA Analog Supply Current 27 32 mA IDDO_X Output Supply Current Outputs in High-Impedance 1 3 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDXTAL XTAL Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.064 3.3 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 136 14 9 mA IDDXTAL XTAL Power Supply Current 40 44 mA IDDA Analog Supply Current 27 32 mA IDDO_X Output Supply Current Outputs in High-Impedance 1 3 mA

REVISION 1 6/16/14 11 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 5C. Power Supply DC Characteristics, VDD = VDDXTAL = 3.3V ± 5%, VDDO_X = 1.8V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF0,VDDO_REF1. NOTE: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF0 + IDDO_REF1 Table 5D. Power Supply DC Characteristics, VDD = VDDXTAL = VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C NOTE: VDDOx denotes, VDDO_A, VDDO_B, VDDO_C,VDDO_REF0,VDDO_REF1. NOTE: IDDOx denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF0 + IDDO_REF1.. Table 5E. Power Supply DC Characteristics, VDD = VDDXTAL = 2.5V ± 5%, VDDO_X = 1.8V ± 5%, TA = -40°C to 85°C NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C,VDDO_REF0,VDDO_REF1. NOTE: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF0 + IDDO_REF1. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 3.135 3.3 3.465 V VDDXTAL XTAL Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.064 3.3 V DD V VDDO_X Output Supply Voltage 1.71 1.8 1.8 9 V IDD Power Supply Current 136 14 9 mA IDDXTAL XTAL Power Supply Current 40 44 mA IDDA Analog Supply Current 27 32 mA IDDO_X Output Supply Current Outputs in High-Impedance 1 2 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDXTAL XTAL Power Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.056 2.5 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 135 147 mA IDDXTAL XTAL Power Supply Current 3 9 43 mA IDDA Analog Supply Current 24 28 mA IDDO_X Output Supply Current Outputs in High-Impedance 1 3 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VDDXTAL XTAL Power Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage V DD – 0.056 2.5 V DD V VDDO_X Output Supply Voltage 1.71 1.8 1.8 9 V IDD Power Supply Current 135 147 mA IDDXTAL XTAL Power Supply Current 3 9 43 mA IDDA Analog Supply Current 24 28 mA IDDO_X Output Supply Current Outputs in High-Impedance 1 2 mA

REVISION 1 6/16/14 12 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 5F. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C NOTE: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C,VDDO_REF0,VDDO_REF1. Table 5G. LVPECL DC Characteristics, VDD = VDDXTAL = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Common mode voltage is defined as VIH. NOTE 2: VIL should not be less than -0.3V and VIH should not be greater than VDD. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V ± 5% 2 V DD + 0.3 V VDD = 2.5V ± 5% 1.7 V DD + 0.3 V VIL Input Low Voltage IIH Input High Current REF_SEL, MR, FSEL[3:0], SSC_EN, REFOUT_SEL,SADR V DD = VIN = 3.465V or 2.625V 150 µA OE_A, OE_B, OE_C, OE_REF, PLL_SEL VDD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current REF_SEL, MR, FSEL[3:0], SSC_EN, REFOUT_SEL,SADR VDD = 3.465V or 2.625V, VIN = 0V -5 µA OE_A, OE_B, OE_C, OE_REF, PLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage VDDO_X = 3.3V ± 5%; IOH = -12mA 2.6 V VDDO_X = 2.5V ± 5%; IOH = -12mA 1.8 V VDDO_X = 1.8V ± 5%; IOH = -8mA 1.3 V VOL Output Low Voltage; VDDO_X = 3.3V ±5% or 2.5V ± 5%, IOL = 12mA 0.5 V VDDO _X = 1.8V ± 5%, IOL = 8mA 0.4 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current PCLK, nPCLK V DD = VIN = 3.465V 150 µA IIL Input Low Current PCLK V DD = 3.465V, VIN = 0V -5 µA nPCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 2 0.3 1.0 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 V DD V

Table 6. Input Frequency Characteristics, VDD = VDDXTAL = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Table 7. Crystal Characteristics

REVISION 1 6/16/14 14 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 8A. AC Characteristics (QA, QBx, QCx), VDD = VDDXTAL = 3.3V ± 5% or 2.5V ± 5%, VDDO_A, VDDO_B, VDDO_C = 3.3V ± 5% or 2.5V ± 5% or 1.8V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: VDDO  VDD. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Jitter performance using XTAL inputs. NOTE 4: Characterized for frequencies in Table 3A. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units f OUT Output Frequency 25 200 MHz tsk(b) Bank Skew; NOTE 1, 2, 4 70 ps ()N Single Side-Band Phase Noise; NOTE 4 Offset from Carrier: 500kHz -140 dBc tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3, 4 VDDO = 3.3V FSEL[3:0] = 0000, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1101, 1111 90 300 ps FSEL[3:0] = 0001, 0111, 1000, 1011, 1100, 1110 260 530 ps VDDO = 2.5V FSEL[3:0] = 0000, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1101, 1111 60 250 ps FSEL[3:0] = 0001, 0111, 1000, 1011, 1100, 1110 200 400 ps VDDO = 1.8V FSEL[3:0] = 0000, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1101, 1111 60 200 ps FSEL[3:0] = 0001, 0111, 1000, 1011, 1100, 1110 175 350 ps tjit(per) Period Jitter, Peak; NOTE 1, 3, 4 VDDO = 3.3V FSEL[3:0] = 0000, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1101, 1111 ±150 ps FSEL[3:0] = 0001, 0111, 1000, 1011, 1100, 1110 ±265 ps VDDO = 2.5V FSEL[3:0] = 0000, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1101, 1111 ±125 ps FSEL[3:0] = 0001, 0111, 1000, 1011, 1100, 1110 ±200 ps VDDO = 1.8V FSEL[3:0] = 0000, 0010, 0011, 0100, 0101, 0110, 1001, 1010, 1101, 1111 ±100 ps FSEL[3:0] = 0001, 0111, 1000, 1011, 1100, 1110 ±175 ps tL PLL Lock Time; NOTE 4 50 ms odc Output Duty Cycle; NOTE 4 40 60 % tsl(o) Slew Rate; NOTE 4

REVISION 1 6/16/14 15 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Table 8B. AC Characteristics (QREF[0:1]), VDD = VDDXTAL = 3.3V ± 5% or 2.5V ± 5%, VDDO_REF0, VDDO_REF1 = 3.3V ± 5% or NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: VDDO  VDD. NOTE 1: Crystal oscillator selected as frequency source. NOTE 2: Refer to phase noise plot. Only applies to QREF1. NOTE 3: Input duty cycle must be 50%. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency; NOTE 1 QREF0 1.5625 3.125 MHz QREF1 25 MHz tjit() RMS Phase Jitter (Random); NOTE 1, 2 QREF1 fOUT = 25MHz, Integration Range: 12kHz to 5MHz 0.218 0.312 ps odc Output Duty Cycle; NOTE 3 40 60 % tsl(o) Slew Rate QREF1, fOUT = 25MHz

REVISION 1 6/16/14 16 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Typical Phase Noise at 25MHz (QREF1 output at 3.3V) Noise Power (dBc/Hz) Offset Frequency (Hz)

REVISION 1 6/16/14 17 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Typical Single-side Band Phase Noise (QB output at 3.3V) Noise Power (dBc/Hz) Offset Frequency (Hz)

REVISION 1 6/16/14 18 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit 3.3V Core/2.5V LVCMOS Output Load Test Circuit 2.5V Core/1.8V LVCMOS Output Load Test Circuit 2.5V Core/2.5V LVCMOS Output Load Test Circuit 3.3V Core/1.8V LVCMOS Output Load Test Circuit Differential Input Level SCOPE Qx GND VDD, -1.65V±5% 1.65V±5% VDDO_X VDDA 1.65V±5% VDDXA, SCOPE Qx GND VDD, -1.25V±5% 2.05V±5% VDDO_X 1.25V±5% VDDA 2.05V±5% VDDXA SCOPE Qx GND VDD, -0.9V±5% 1.6V±5% VDDO_X 0.9V±5% VDDA 1.6V±5% VDDXA SCOPE Qx GND VDD, -1.25V±5% 1.25V±5% VDDO_X 1.25V±5% VDDA VDaDXA, SCOPE Qx GND VDD, -0.9V±5% 2.4V±5% VDDO_X 0.9V±5% 2.4V±5% VDDA VDDXA VDD GND V CMR Cross Points VPP PCLK PCLK

REVISION 1 6/16/14 19 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Parameter Measurement Information, continued RMS Period Jitter, Peak-to-Peak Bank Skew Output Duty Cycle/Pulse Width/Period PLL Lock Time Slew Rate VOH VREF VOL Mean Period (First edge after trigger) 10,000 cycles Reference Point (Trigger Edge) Histogram t jit (pk-pk) tsk(b) VDDO_X VDDO_X QXx QXx Where X = Bank B, or C tPERIOD tPW tPERIOD odc = VDDO_X x 100% tPW QA, QBx, QCx, QREFx tR tF VFVR 0.35VDDO_X 0.65VDDO_X 0.65VDDO_X 0.35VDDO_X QREF[0:1], QA, QBx, QCx

REVISION 1 6/16/14 20 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Applications Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. PCLK/nPCLK Inputs For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. There should be no trace attached.

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

REVISION 1 6/16/14 24 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS Schematic Layout Figure 5 shows an example 840NT4 application schematic. This schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In this schematic, the device is operated at VDD = VDDA = 2.5V and VDDO_A, VDDO_B, VDDO_C and VDDO_REFx = 1.8V. A 12pF parallel resonant 25MHz crystal is used with the recommended load capacitors C1 = C2 = 3.3pF for frequency accuracy. Depending on the parasitic capacity on the crystal terminals of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. Crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board. Capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. Routing I 2C under the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. In fact, I2C transition times are short enough to capacitively couple into the crystal if they are routed close enough to the crystal traces. In layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the XTAL_IN and XTAL_OUT pins, traces to the crystal pads, the crystal pads and the tuning capacitors. Using a crystal on the top layer as an example, void all signal and power layers under the crystal connections between the top layer and the ground plane used by the 840NT4. Then calculate the parasitic capacity to the ground and determine if it is large enough to preclude tuning the oscillator. If the coupling is excessive, particularly if the first layer under the crystal is a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. The ground connection of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning cap ground to the ground plane as close to the 840NT4 as possible as shown in the schematic. This device package has an ePAD that is connected to ground internally. The ePAD is to be connected to V EE/GND through vias in order to improve heat dissipation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 840NT4 provides separate power supply pins to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. For additional layout recommendations and guidelines, contact clocks@idt.com.

Figure 5. 840NT4 Schematic Layout

15 OE_A

25 MHz

This section provides information on power dissipation and junction temperature for the 840NT4. Equations and example calculations are also provided. DD = 3.3V +5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 29°C/W per Table 9 below. Table 9. Thermal Resistance JA for a 48 Lead VFQFN Package, Forced Convection

Table 10. JA vs. Air Flow Table for a 48 Lead VFQFN

REVISION 1 6/16/14 28 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS

48 Lead VFQFN Package Outline and Package Dimensions

REVISION 1 6/16/14 29 SYSTEM & DD R CLOCKS FOR FREESCALE B4/T4 PROCESSOR SYSTEMS

Ordering Information

Table 11. Ordering Information NOTE: Parts that are ordered with an "G" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

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