840NT4-01 IDT | Alldatasheet
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Technical content
Features
Ten LVCMOS clock outputs: Five LVCMOS 125MHz Ethernet outputs Three LVCMOS 25MHz /125MHz Ethernet outputs One LVCMOS 24MHz USB output One LVCMOS 25MHz REF output QREF output can be used to drive other clock drivers, saving a crystal Selectable crystal or differential LVPECL input RMS Phase Jitter, 125MHz, integration range 12kHz - 20MHz: 0.60ps (typical) Cycle-to-Cycle jitter: 20ps (typical) Flexible voltage supply modes; supports legacy and future system requirements, minimizes power consumption Core voltage: VDD, VDD_XTAL, VDDA Output voltage: VDDO_A, VDDO_B, VDDO_C, VDDO_REF Core / Output 3.3V / 3.3V 3.3V / 2.5V 3.3V / 1.8V 2.5V / 2.5V 2.5V / 1.8V Table 1. Output Frequency Table *PD = Phase Detector input frequency.
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS
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÷M ÷M Femtoclock®NG VDDA QA2 PDIV_SEL Pulldown PLL_SELA QA3 QA4 ÷N1 OE_B OE_A Pullup Pullup VDDO_A VDDO_B VDD QA0 QA1 QB0 QB1 XTAL_IN XTAL_OUT OSC25MHz QB2 QC VDDO_C QREF VDDO_REF ÷NFRAC Pullup OE_REF Pullup OE_C PCLK nPCLK Pullup/ Pulldown Pulldown XTAL_SEL Pulldown PLL_SELB Pullup Pullup ÷N2 PSELB Pulldown 24MHz 125MHz 125MHz/ 25MHz 25MHz
Table 2. Pin Descriptions
1 XTAL_IN Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
2 XTAL_OUT Input
3V DD_XTAL Power Power supply pin for XTAL. 6 GND Power Power supply ground. 7V DD Power Core supply pins.
8 PDIV_SEL Input Pulldown
Selects input for PCLK (LOW) or 5 pre-divider (HIGH). LVCMOS/LVTTL interface levels. 9 GND_DSM Power Ground pin for Delta Sigma Modulator. on disable. LVCMOS/LVTTL interface levels. 11 V DDO_REF Power Output power supply for QREF output. 12 QREF Output Single-ended 25MHz, reference clo ck output. LVCMOS/LVTTL interface levels. 13 GND_REF Power Ground pin for QREF clock output. mode on disable. LVCMOS/LVTTL interface levels. 15 GND_QC Power Ground pin for QC clock output. 16 QC Output Single-ended 24MHz, USB clock output. LVCMOS/LVTTL interface levels. 17 V DDO_C Power Output power supply for QC output. high-impedance mode on disable. LVCMOS/LVTTL interface levels. 19 VDDO_B Power Output power supply for Bank QBx clock outputs.
20 QB2 Output
22 QB0 Output
23 V DDO_B Power Output power supply for Bank QBx clock outputs. 24 GND_QB Power Ground pin for Bank QBx clock outputs. 25 GND Power Power supply ground. 26 GND_QA Power Ground pin for Bank QAx clock outputs.
27 QA4 Output
29 QA2 Output
30 V DDO_A Power
Output power supply for Bank QAx clock outputs.
31 V DDO_A Power
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high-impedance mode on disable. LVCMOS/LVTTL interface levels. 35 GND_QA Power Ground pin for Bank QAx clock outputs. 36 GND Power Power supply ground. 37 V DD Power Core supply pins.
38 PSELB Input Pulldown
(LOW) or phase detector input frequency (HIGH). LVCMOS/LVTTL interface levels. 39 PLL_SELA Input Pullup Bypasses the PLL for Bank A outputs. When LOW, selects PLL (PLL Enable). When HIGH, bypasses the PLL. LVCMOS/LVTTL interface levels.
40 PLL_SELB Input Pullup
41 GNDA Power Ground pin for PLL analog. 42 V DDA Power Analog supply pin. 43 GND Power Power supply ground. 44 V DD Power Core supply pins. 45 RESERVED Reserved Reserved pin. Do not connect. 46 V DD Power Core supply pins.
47 XTAL_SEL Input Pulldown
Select input for XTAL (LOW) or PCLK pre-divider (HIGH). LVCMOS/LVTTL interface levels. 48 GND_XTAL Power Ground pin for XTAL. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Descriptions1 (Continued) Table 3. Pin Characteristics1 NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF .
REVISION 2 05/18/15 5 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical Characteristicsis not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO_X + 0.5V Junction Temperature 125C Storage Temperature, TSTG -65C to 150C NOTE: VDDO_X denotes VDDO_A, VDDO_B, VDDO_C & VDDO_REF . Table 4A. Power Supply DC Characteristics, VDD = VDD_XTAL = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C1, 2 Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDD_XTAL XTAL Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.06 3.3 V DD V VDDO_X Output Supply Voltage 3.135 3.3 3.465 V IDD + IDD_XTAL Power Supply Current 150 mA IDDA Analog Supply Current 30 mA IDDO_X Output Supply Current Outputs are Disabled to High-Impedance 8m A NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF . NOTE 2: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF . Table 4B. Power Supply DC Characteristics, VDD = VDD_XTAL = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C1, 2 Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDD_XTAL XTAL Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.06 3.3 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD + IDD_XTAL Power Supply Current 150 mA IDDA Analog Supply Current 30 mA IDDO_X Output Supply Current Outputs are Disabled to High-Impedance 4m A NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF . NOTE 2: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF .
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS
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Table 4C. Power Supply DC Characteristics, VDD = VDD_XTAL = 3.3V ± 5%, VDDO_x = 1.8V ± 5%, TA = -40°C to 85°C 1, 2 Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDD_XTAL XTAL Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.06 3.3 V DD V VDDO_X Output Supply Voltage 1.71 1.8 1.8 9 V IDD + IDD_XTAL Power Supply Current 150 mA IDDA Analog Supply Current 30 mA IDDO_X Output Supply Current Outputs are Disabled to High-Impedance 3m A NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF . NOTE 2: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF . Table 4D. Power Supply DC Characteristics, VDD = VDD_XTAL = VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C1, 2 Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDD_XTAL XTAL Power Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD – 0.054 2.5 V DD V VDDO_X Output Supply Voltage 2.375 2.5 2.625 V IDD + IDD_XTAL Power Supply Current 148 mA IDDA Analog Supply Current 27 mA IDDO_X Output Supply Current Outputs are Disabled to High-Impedance 4m A NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF . NOTE 2: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF . Table 4E. Power Supply DC Characteristics, VDD = VDD_XTAL = 2.5V ± 5%, VDDO_X = 1.8V ± 5%, TA = -40°C to 85°C1, 2 Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDD_XTAL XTAL Power Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage VDD – 0.054 2.5 V DD V VDDO_X Output Supply Voltage 1.71 1.8 1.8 9 V IDD + IDD_XTAL Power Supply Current 148 mA IDDA Analog Supply Current 27 mA IDDO_X Output Supply Current Outputs are Disabled to High-Impedance 3m A NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF . NOTE 2: IDDO_X denotes, IDDO_A + IDDO_B + IDDO_C + IDDO_REF .
REVISION 2 05/18/15 7 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS Table 4F. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C1 NOTE 1: VDDO_X denotes, VDDO_A, VDDO_B, VDDO_C, VDDO_REF . Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V ± 5% 2 V DD + 0.3 V VDD = 2.5V ± 5% 1.7 V DD + 0.3 V VIL Input Low Voltage IIH Input High Current PSELB, XTAL_SEL, PDIV_SEL VDD = VIN = 3.465V or 2.625V 150 µA OE_REF, PLL_SELA, PLL_SELB, OE_A, OE_B, OE_C VDD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current PSELB, XTAL_SEL, PDIV_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA OE_REF, PLL_SELA, PLL_SELB, OE_A, OE_B, OE_C VDD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage VDDO_X = 3.3V ± 5%; IOH = -12mA 2.6 V VDDO_X = 2.5V ± 5%; IOH = -12mA 1.8 V VDDO_X = 1.8V ± 5%; IOH = -8mA 1.3 V VOL Output Low Voltage; VDDO_X= 3.3V ± 5%, IOL = 12mA 0.5 V VDDO_X= 2.5V ± 5%, IOL = 12mA 0.5 V VDDO_X = 1.8V ± 5%, IOL = 8mA 0.4 V Table 4G. LVPECL Differential DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK, nPCLK V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current PCLK VDD = 3.465V or 2.625V, VIN = 0V -5 µA nPCLK VDD = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 1 0.3 1.0 V VCMR Common Mode Input Voltage1, 2 GND + 1.5 V DD V NOTE 1: VIL should not be less than -0.3V and VIH should not be greater than VDD.. NOTE 2: Common mode voltage is defined at the crosspoint.
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Table 5. Input Frequency Characteristics, VDD = VDD_XTAL = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Table 6. Crystal Characteristics1 NOTE 1: IDT Part#603-25-173 recommended.
Table 7. AC Characteristics, VDD = VDD_XTAL = 3.3V ± 5% or 2.5V ± 5%, VDDO_A, VDDO_B, VDDO_C, VDDO_REF = 3.3V ± 5% equilibrium has been reached under these conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 5: Jitter performance using XTAL inputs. NOTE 6: Measured with Bank A at 125MHz, Bank B at 125MHz, QC and QREF enabled.
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS
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Typical Phase Noise at 125MHz Noise Power (dBc/Hz) Offset Frequency (Hz)
REVISION 2 05/18/15 11 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit 3.3V Core/2.5V LVCMOS Output Load Test Circuit 2.5V Core/1.8V LVCMOS Output Load Test Circuit 2.5V Core/2.5V LVCMOS Output Load Test Circuit 3.3V Core/1.8V LVCMOS Output Load Test Circuit Differential Input Level SCOPE Q GND VDD, -1.65V±5% 1.65V±5% VDDO_X VDDA 1.65V±5% VDD_XTAL, SCOPE Qx GND VDD, -1.25V±5% 2.05V±5% VDDO_X 1.25V±5% VDDA 2.05V±5% VDD_XTAL SCOPE Qx GND VDD, -0.9V±5% 1.6V±5% VDDO_X 0.9V±5% VDDA 1.6V±5% VDD_XTAL SCOPE Q GND VDD, -1.25V±5% 1.25V±5% VDDO_X 1.25V±5% VDDA VDD_XTAL, SCOPE Qx GND VDD, -0.9V±5% 2.4V±5% VDDO_X 0.9V±5% 2.4V±5% VDDA VDD_XTAL VDD GND PCLK nPCLK
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS
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Parameter Measurement Information, continued RMS Phase Jitter RMS Period Jitter Bank Skew Output Duty Cycle/Pulse Width/Period PLL Lock Time Cycle-to-Cycle Jitter Output Skew Output Rise Fall Time VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram tsk(b) VDDO_X VDDO_X QXx QXy tPERIOD tPW tPERIOD odc = VDDO_X x 100% tPW QAx, QBx, QC ➤➤ ➤➤ VDDO_X VDDO_X VDDO_X tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
QAx, QBx tsk(o) VDDOX VDDOX QXx QXy 20% 80% 80% 20% tR tF QAx, QBx, QC
REVISION 2 05/18/15 13 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS Applications Information Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. PCLK/nPCLK Inputs For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. Outputs: LVCMOS Outputs All unused LVCMOS outputs can be left floating. There should be no trace attached.
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS
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Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface VDD XTA L_OUT XTA L_IN 100 100 Zo = 50 ohms RsRo Zo = Ro + Rs .1uf LVCMOS Driver XTAL_OU T XTAL_I N Zo = 50 ohms C2 .1uf LVPECL Driver Zo = 50 ohms 50R3
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Figure 4. The solderable area on the PCB, as and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
REVISION 2 05/18/15 17 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS Schematic Example Figure 5 (next page) shows an example 840NT4-01 application schematic. This schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. In this schematic, the device is operated at VDD = VDDA = 2.5V and VDDO_A, VDDO_B, VDDO_C and VDDO_REF = 1.8V. A 12pF parallel resonant 25MHz crystal (IDT/ Fox Part #603-25-173) is used with the recommended load capacitors C1 = C2 = 3.3pF for frequency accuracy. Depending on the parasitic capacity on the crystal terminals of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. Crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board. Capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. Routing I2C under the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. In fact, I2C transition times are short enough to capacitively couple into the crystal if they are routed close enough to the crystal traces. In layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the XTAL_IN and XTAL_OUT pins, traces to the crystal pads, the crystal pads and the tuning capacitors. Using a crystal on the top layer as an example, void all signal and power layers under the crystal connections between the top layer and the ground plane used by the 840NT4-01. Then calculate the parasitic capacity to the ground and determine if it is large enough to preclude tuning the oscillator. If the coupling is excessive, particularly if the first layer under the crystal is a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. The ground connection of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning cap ground to the ground plane as close to the 840NT4-01 as possible as shown in the schematic. This device package has an ePAD that is connected to ground internally. The ePAD is to be connected to VEE/GND through vias in order to improve heat dissipation. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 840NT4-01 provides separate power supply pins to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1F capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. For additional layout recommendations and guidelines, contact clocks@idt.com.
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Figure 5. 840NT4-01 Schematic Layout
25 MHz
14 OE_B
18 OE_A
38 PLL_SELA
Equations and example calculations are also provided. is the power dissipation for VDD = 3.3V +5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. Table 8. Thermal Resistance JA for a 48-lead VFQFN Package
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Table 9. JA vs. Air Flow Table for a 48-Lead VFQFN
REVISION 2 05/18/15 21 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS 48-Lead VFQFN Package Outline and Package Dimensions
ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS
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Ordering Information
Table 10. Ordering Information
REVISION 2 05/18/15 23 ETHERNET & USB CLOCK GENERATOR FOR FREESCALE B4/T4-BASED SYSTEMS Revision History Sheet Rev Table Page Description of Change Date Crystal Characteristics - added note. Schematic Example - revised first sentence of paragraph 2. 840NT4-01 Schematic Layout - revised crystal note. 5/18/15
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