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Technical content
Features
- Fourth generation FemtoClock® NG technology
- 155.52MHz output clock synthesized from a 19.44MHz fundamental mode crystal
- One 2.5V or 3.3V LVCMOS/LVTTL clock output
- Crystal interface designed for a 12pF parallel resonant crystal
- RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 20MHz): 0.482ps (maximum)
- RMS phase jitter @ 156.25MHz, using a 19.53125MHz crystal (1.875MHz - 20MHz): 0.138ps (maximum)
- LVCMOS interface levels for the control inputs
- Full 2.5V or 3.3V supply voltage
- Lead-free (RoHS 6) packaging
- -40°C to 85°C ambient operating temperature OE Function Table NOTE: OE is an asynchronous control FREQ_SEL Frequency Table NOTE: FREQ_SEL is an asynchronous control. Input Output EnableOE
0 Output Q is disabled in high-impedance state
1 (default) Output Q is enabled. Input Output Frequency FREQ_SEL f XTAL = 19.2MHz f XTAL = 19.44MHz f XTAL = 19.53125MHz 0 (default) 153.6MHz 155.52MHz 156.25MHz 1 76.8MHz 77.76MHz 78.125MHz Block Diagram Pin Assignment ICS840N051I 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
8 VDD
6 GND
5 FREQ_SEL
XTAL_OUT 3 XTAL_IN 4 Pulldown OSC XTAL_IN XTAL_OUT FREQ_SEL OE ÷32 ÷4, PFD LPF FemtoClock® NG VCO 490-637.5MHz Q Pullup
ICS840N051BGI REVISION A OCTOBER 14, 2013 2 ©2013 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Power Analog power supply. 2 OE Input Pullup Output enable pin. LVCMOS interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS interface levels. 6 GND Power Power supply ground. 7 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels.
ICS840N051BGI REVISION A OCTOBER 14, 2013 3 ©2013 Integrated Device Technology, Inc. ICS840N051I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C NOTE 1: Output terminated with 50 to VDD / 2. See Parameter Measurement Information Section, LVCMOS Output Load Test Circuit Diagrams. Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 117°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.18 3.3 V DD V VDDA Analog Supply Voltage V DD – 0.18 2.5 V DD V IDDA Analog Supply Current 18 mA IDD Power Supply Current 67 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage FREQ_SEL V DD = 3.3V -0.3 0.5 V OE V DD = 3.3V -0.3 0.8 V FREQ_SEL V DD = 2.5V -0.3 0.5 V OE V DD = 2.5V -0.3 0.7 V IIH Input High Current FREQ_SEL V DD = VIN = 3.465V or 2.625V 150 µA OE V DD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current FREQ_SEL V DD = 3.465V or 2.625V, VIN = 0V -5 µA OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 Q VDD = 3.465V 2.6 V VDD = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 QV DD = 3.465V or 2.625V 0.5 V
ICS840N051BGI REVISION A OCTOBER 14, 2013 4 ©2013 Integrated Device Technology, Inc. Table 4. Crystal Characteristics Table 5. AC Characteristics, VDD = VDDA = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: Characterized with 19.2MHz, 19.44MHz and 19.53125MHz crystals. NOTE 1: Please refer to the phase noise plots.
ICS840N051BGI REVISION A OCTOBER 14, 2013 5 ©2013 Integrated Device Technology, Inc. ICS840N051I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER Typical Phase Noise at 77.76MHz Typical Phase Noise at 155.52MHz Noise Power(dBc/Hz) Offset Frequency (Hz) Noise Power(dBc/Hz) Offset Frequency (Hz)
ICS840N051BGI REVISION A OCTOBER 14, 2013 6 ©2013 Integrated Device Technology, Inc. ICS840N051I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER Typical Phase Noise at 156.25MHz Noise Power(dBc/Hz) Offset Frequency (Hz)
ICS840N051BGI REVISION A OCTOBER 14, 2013 7 ©2013 Integrated Device Technology, Inc. ICS840N051I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER Parameter Measurement Information 2.5V LVCMOS/LVTTL Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period 3.3V LVCMOS/LVTTL Output Load AC Test Circuit Output Rise/Fall Time SCOPE Qx GND VDD 1.25V ± 5% -1.25V ± 5% VDDA 1.25V ± 5% tPERIOD tPW tPERIOD odc = VDD x 100% tPW Q SCOPE Qx GND VDD 1.65V ± 5% -1.65V ± 5% VDDA 1.65V ± 5% Q 20% 80% 80% 20% tR tF
ICS840N051BGI REVISION A OCTOBER 14, 2013 10 ©2013 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS840N051I. Equations and example calculations are also provided. The total power dissipation for the ICS840N051I is the sum of the core power plus the analog power plus the power dissipated into the load. DD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 117°C/W per Table 6 below. Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
ICS840N051BGI REVISION A OCTOBER 14, 2013 11 ©2013 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 8-lead TSSOP
ICS840N051BGI REVISION A OCTOBER 14, 2013 12 ©2013 Integrated Device Technology, Inc. ICS840N051I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Ordering Information
Table 9. Ordering Information
ICS840N051BGI REVISION A OCTOBER 14, 2013 13 ©2013 Integrated Device Technology, Inc. ICS840N051I Data Sheet FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER Revision History Sheet Rev Table Page Description of Change Date A 1 General Description - corrected output frequ ency of 156.25MHz to 155.52MHz in second sentence. 10/14/2013
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi- cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved.
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