DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 13

Technical content

Features

  • Fourth generation FemtoClock® NG technology
  • 125MHz output clock synthesized from a 25MHz fundamental mode crystal
  • One LVCMOS/LVTTL clock output
  • Crystal interface designed for a 12pF parallel resonant crystal
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.148ps (maximum)
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (12kHz - 20MHz): 0.479ps (maximum)
  • LVCMOS interface levels for the control inputs
  • Full 2.5V or 3.3V supply voltage
  • Lead-free (RoHS 6) packaging
  • -40°C to 85°C ambient operating temperature
  • Use replacement part: 840N202CKI-dddLF Input Output Frequency FREQ_SEL f XTAL = 25MHz f XTAL = 20MHz 0 (default) 125MHz 100MHz 1 62.5MHz 50MHz Input Output EnableOE

0 Output Q is disabled in high-impedance state

1 (default) Output Q is enabled. Block Diagram Pin Assignment 840N022 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View

8 VDD

6 GND

5 FREQ_SEL

XTAL_OUT 3 XTAL_IN 4 Pulldown OSC XTAL_IN XTAL_OUT FREQ_SEL OE ÷25 ÷5, ÷10 PFD LPF FemtoClock® NG VCO 490-637.5MHz Q Pullup

2 REVISION A 8/14/15

Table 1. Pin Descriptions NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Power Analog power supply. 2 OE Input Pullup Output enable pin. LVCMOS interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 FREQ_SEL Input Pulldown Frequency select pin. LVCMOS interface levels. 6 GND Power Power supply ground. 7 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 8V DD Power Core supply pin.

REVISION A 8/14/15 3 FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER 840N022 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C NOTE 1: Output terminated with 50 to VDD / 2. See Parameter Measurement Information Section, LVCMOS Output Load Test Circuit Diagrams. Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to V DD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 117°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditi ons Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.18 3.3 V DD V IDDA Analog Supply Current 18 mA IDD Power Supply Current 67 mA Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage OE V DD = 3.3V -0.3 0.8 V FREQ_SEL V DD = 3.3V -0.3 0.5 V OE V DD = 2.5V -0.3 0.7 V FREQ_SEL V DD = 2.5V -0.3 0.5 V IIH Input High Current OE V DD = VIN = 3.465V or 2.625V 5 µA FREQ_SEL V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current OE V DD = 3.465V or 2.625V, VIN = 0V -150 µA FREQ_SEL V DD = 3.465V or 2.625V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 Q VDD = 3.465V 2.6 V VDD = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 QV DD = 3.465V or 2.625V 0.5 V

4 REVISION A 8/14/15

Table 4. Crystal Characteristics Table 5. AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: Characterized with 20MHz and 25MHz crystals. NOTE 1: Please refer to the phase noise plots.

REVISION A 8/14/15 5 FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER 840N022 DATA SHEET Typical Phase Noise at 125MHz Typical Phase Noise at 125MHz Noise Power(dBc/Hz) Offset Frequency (Hz) Noise Power(dBc/Hz) Offset Frequency (Hz)

FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER

6 REVISION A 8/14/15

Parameter Measurement Information 2.5V LVCMOS/LVTTL Output Load Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period 3.3V LVCMOS/LVTTL Output Load Test Circuit Output Rise/Fall Time SCOPE Qx GND VDD 1.25V ± 5% -1.25V ± 5% VDDA 1.25V ± 5% Q SCOPE Qx GND VDD 1.65V ± 5% -1.65V ± 5% VDDA 1.65V ± 5% Q 20% 80% 80% 20% tR tF

8 REVISION A 8/14/15

can be fine tuned to center the oscillator center frequency. filter components can be on the opposite side of the PCB. Figure 2. 840N022 Schematic Example

This section provides information on power dissipation and junction temperature for the 840N022. Equations and example calculations are also provided. DD = 3.3V + 5% = 3.465V, which gives worst case results.

  • Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(67mA + 18mA) = 294.53mW
  • Output Impedance R OUT Current due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA
  • Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW
  • Total Power (R OUT) = 10.7mW * 1 = 10.7mW Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDD)2 = 11pF * 125MHz * (3.465V)2 = 16.51mW Total Power (125MHz) = 16.51mW * 1 = 16.51mW Total Power Dissipation
  • Total Power = Power (core)MAX + Power (ROUT) + Power (125MHz) = 294.53mW + 10.7mW + 16.51mW = 321.74mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 117°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.322W *117°C/W = 122.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection

10 REVISION A 8/14/15

Table 7. JA vs. Air Flow Table for a 8-lead TSSOP

REVISION A 8/14/15 11 FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER 840N022 DATA SHEET

Ordering Information

Table 9. Ordering Information

FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER

12 REVISION A 8/14/15

Rev Table Page Description of Change Date A Product Discontinuation Notice - Last time buy expires August 14, 2016 PDN CQ-15-04 8/14/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com Tech Support email: clocks@idt.com