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Document overview
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- PDF pages: 13
Technical content
Features
- Fourth generation FemtoClock® NG technology
- 125MHz output clock synthesized from a 25MHz fundamental mode crystal
- One 2.5V or 3.3V LVCMOS/LVTTL clock output
- Crystal interface designed for a 12pF parallel resonant crystal
- RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.156ps (maximum)
- RMS phase jitter @ 100MHz, using a 20MHz crystal (12kHz - 20MHz): 0.451ps (maximum)
- LVCMOS interface level for the output enable input
- Full 2.5V or 3.3V supply voltage
- Lead-free (RoHS 6) packaging
- -40°C to 85°C ambient operating temperature
- Use replacement part 840N202CKI-dddLFfXTAL (MHz) Q Output Frequency (MHz) 20 100 25 125 Input Output EnableOE
0 Output Q is disabled in high-impedance state
1 (default) Output Q is enabled. Pin Assignment 840N021 8-lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
8 VDD
6 GND
5 DNU
XTAL_OUT 3 XTAL_IN 4 OSC XTAL_IN XTAL_OUT OE ÷25 PFD LPF FemtoClock® NG VCO 490-637.5MHz Pullup Q Block Diagram
Table 1. Pin Descriptions NOTE: Pullup refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1V DDA Power Analog power supply. 2 OE Input Pullup Output enable pin. LVCMOS interface levels. XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 5 DNU Do not use. Do not connect. 6 GND Power Power supply ground. 7 Q Output Single-ended clock output. LVCMOS/LVTTL interface levels. 8V DD Power Core supply pin.
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
3 REVISION A 8/14/15
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3A. Power Supply DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C NOTE 1: Output terminated with 50 to VDD / 2. See Parameter Measurement Information Section, LVCMOS Output Load Test Circuit Diagrams. Item Rating Supply Voltage, VDD 3.63V Inputs, VI XTAL_IN Other Inputs 0V to 2V -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 117°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.18 3.3 V DD V VDDA Analog Supply Voltage V DD – 0.18 2.5 V DD V IDDA Analog Supply Current 18 mA IDD Power Supply Current 67 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current OE V DD = VIN = 3.465V or 2.625V 5 μA IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V -150 μA VOH Output High Voltage; NOTE 1 Q VDD = 3.465V 2.6 V VDD = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 QV DD = 3.465V or 2.625V 0.5 V
Table 4. Crystal Characteristics Table 5. AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: Characterized with 20MHz and 25MHz crystals. NOTE 1: Please refer to the phase noise plots.
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
5 REVISION A 8/14/15
Typical Phase Noise at 125MHz Typical Phase Noise at 100MHz Noise Power (dBc/Hz) Offset Frequency (Hz) Offset Frequency (Hz) Noise Power (dBc/Hz)
REVISION A 8/14/15 6 FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER 840N021 DATA SHEET Parameter Measurement Information 2.5V LVCMOS/LVTTL Output Load AC Test Circuit RMS Phase Jitter Output Duty Cycle/Pulse Width/Period 3.3V LVCMOS/LVTTL Output Load AC Test Circuit Output Rise/Fall Time SCOPE Qx GND VDD 1.25V ± 5% -1.25V ± 5% VDDA 1.25V ± 5% Q SCOPE Qx GND VDD 1.65V ± 5% -1.65V ± 5% VDDA 1.65V ± 5% Q 20% 80% 80% 20% tR tF
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
7 REVISION A 8/14/15
Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 1A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 1B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
9 REVISION A 8/14/15
This section provides information on power dissipation and junction temperature for the 840N021. Equations and example calculations are also provided. DD = 3.3V + 5% = 3.465V, which gives worst case results.
- Power (core) MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(67mA + 18mA) = 294.53mW
- Output Impedance R OUT Current due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA
- Power Dissipation on the R OUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output
- Total Power (R OUT) = 10.7mW * 1 = 10.7mW Dynamic Power Dissipation at 125MHz Power (125MHz) = CPD * Frequency * (VDD)2 = 11pF * 125MHz * (3.465V)2 = 16.51mW per output Total Power (125MHz) = 16.51mW * 1 = 16.51mW Total Power Dissipation
- Total Power = Power (core)MAX + Power (ROUT) + Power (125MHz) = 294.53mW + 10.7mW + 16.51mW = 321.74mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 117°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.322W *117°C/W = 122.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
Table 6. JA vs. Air Flow Table for a 8-lead TSSOP
11 REVISION A 8/14/15
Table 8. Ordering Information
REVISION A 8/14/15 12 FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER 840N021 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date A Product Discontinuation Notice - Last time buy expires August 14, 2016 PDN CQ-15-04 8/14/15
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