SN54HC273 TI | Alldatasheet
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/C0083/C0078/C0053/C0052/C0072/C0067/C0050/C0055/C0051/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0050/C0055/C0051 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Wide Operating Voltage Range of 2 V to 6 V /C0068Outputs Can Drive Up To 10 LSTTL Loads /C0068Low Power Consumption, 80-µA Max ICC /C0068Typical tpd = 12 ns /C0068±4-mA Output Drive at 5 V /C0068Low Input Current of 1 µA Max /C0068Contain Eight Flip-Flops With Single-Rail Outputs /C0068Direct Clear Input /C0068Individual Data Input to Each Flip-Flop /C0068Applications Include: − Buffer/Storage Registers − Shift Registers − Pattern Generators
description
V CC CLK SN54HC273 ...J O R W PACKAGE SN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 3212 0 1 9 91 01 11 2 1 3 CLR 5D 8Q GND CLK VCC SN54HC273 . . . FK PACKAGE (TOP VIEW) description/ordering information These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 20 SN74HC273N SN74HC273N SOIC − DW Tube of 25 SN74HC273DW HC273SOIC − DW Reel of 2000 SN74HC273DWR HC273 −40°C to 85°C SOP − NS Reel of 2000 SN74HC273NSR HC273 −40°C to 85°C SSOP − DB Reel of 2000 SN74HC273DBR HC273 Tube of 70 SN74HC273PW TSSOP − PW Reel of 2000 SN74HC273PWR HC273TSSOP − PW Reel of 250 SN74HC273PWT HC273 CDIP − J Tube of 20 SNJ54HC273J SNJ54HC273J −55°C to 125°C CFP − W Tube of 85 SNJ54HC273W SNJ54HC273W−55 C to 125C LCCC − FK Tube of 55 SNJ54HC273FK SNJ54HC273FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 /C0079/C0110 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0109/C0112/C0108/C0105/C0097/C0110/C0116 /C0116/C0111 /C0077/C0073/C0076/C0262/C0080/C0082/C0070/C0262/C0051/C0056/C0053/C0051/C0053/C0044 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115 /C0097/C0114/C0101 /C0116/C0101/C0115/C0116/C0101/C0100 /C0117/C0110/C0108/C0101/C0115/C0115 /C0111/C0116/C0104/C0101/C0114/C0119/C0105/C0115/C0101 /C0110/C0111/C0116/C0101/C0100/C0046 /C0079/C0110 /C0097/C0108/C0108 /C0111/C0116/C0104/C0101/C0114 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115/C0044 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0083/C0078/C0053/C0052/C0072/C0067/C0050/C0055/C0051/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0050/C0055/C0051 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued) Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT CLR CLK D OUTPUT Q L X X L H ↑ HH H ↑ LL H L X Q 0 logic diagram (positive logic) CLK R R R R R R R R CLR logic diagram, each flip-flop (positive logic) CLK(I) R Q C C D C C C C C C TG TG TG TG C C
/C0083/C0078/C0053/C0052/C0072/C0067/C0050/C0055/C0051/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0050/C0055/C0051 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC273 SN74HC273 UNITMIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 VVIH High-level input voltage VCC = 6 V 4.2 4.2 V VCC = 2 V 0.5 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 VVIL Low-level input voltage VCC = 6 V 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 1000 1000 ∆t/∆v Input transition rise/fall time VCC = 4.5 V 500 500 ns∆t/∆v Input transition rise/fall time VCC = 6 V 400 400 ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0083/C0078/C0053/C0052/C0072/C0067/C0050/C0055/C0051/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0050/C0055/C0051 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC273 SN74HC273 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 VOH VI = VIH or VIL IOH = −20 µA 6 V 5.9 5.999 5.9 5.9 VVOH VI = VIH or VIL V 2 V 0.002 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 20 µA 6 V 0.001 0.1 0.1 0.1 VVOL VI = VIH or VIL V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA C i 2 V to 6 V 3 10 10 10 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC273 SN74HC273 UNITVCC MIN MAX MIN MAX MIN MAX UNIT
2 V 5 4 4
fclock Clock frequency 4.5 V 27 18 21 MHzfclock Clock frequency
6 V 32 21 25
2 V 80 120 100
CLR low 4.5 V 16 24 20 tw Pulse duration CLR low
6 V 14 20 17
nstw Pulse duration 2 V 80 120 100 ns CLK high or low 4.5 V 16 24 20CLK high or low
2 V 100 150 125
Data 4.5 V 20 30 25 tsu Setup time before CLK↑ Data
6 V 17 25 21
nstsu Setup time before CLK↑ 2 V 100 150 125 ns CLR inactive 4.5 V 20 30 25CLR inactive
2 V 0 0 0
th Hold time, data after CLK↑ 4.5 V 0 0 0 nsth Hold time, data after CLK
6 V 0 0 0
/C0083/C0078/C0053/C0052/C0072/C0067/C0050/C0055/C0051/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0050/C0055/C0051 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM TO VCC TA = 25°C SN54HC273 SN74HC273 UNITPARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT
2 V 5 11 4 4
fmax 4.5 V 27 50 18 21 MHzfmax
6 V 32 60 21 25
2 V 55 160 240 200
tPHL CLR Any 4.5 V 15 32 48 40 nstPHL CLR Any
6 V 12 27 41 34
2 V 56 160 240 200
tpd CLK Any 4.5 V 15 32 48 40 nstpd CLK Any
6 V 13 27 41 34
2 V 38 75 110 95
tt Any 4.5 V 8 15 22 19 nstt Any
6 V 6 13 19 16
operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per flip-flop No load 35 pF
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: A. C L includes probe and test-fixture capacitance. characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms
/C0083/C0078/C0053/C0052/C0072/C0067/C0050/C0055/C0051/C0044 /C0083/C0078/C0055/C0052/C0072/C0067/C0050/C0055/C0051 /C0079/C0067/C0084/C0065/C0076 /C0068/C0262/C0084/C0089/C0080/C0069 /C0070/C0076/C0073/C0080/C0262/C0070/C0076/C0079/C0080/C0083 /C0087/C0073/C0084/C0072 /C0067/C0076/C0069/C0065/C0082 SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 84099012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8409901RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC 8409901SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC JM38510/65601BRA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC JM38510/65601BSA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC SN54HC273J ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC SN74HC273DBLE OBSOLETE SSOP DB 20 None Call TI Call TI SN74HC273DBR ACTIVE SSOP DB 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC273DW ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74HC273DWR ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74HC273N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74HC273N3 OBSOLETE PDIP N 20 None Call TI Call TI SN74HC273NSR ACTIVE SO NS 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74HC273PW ACTIVE TSSOP PW 20 70 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC273PWLE OBSOLETE TSSOP PW 20 None Call TI Call TI SN74HC273PWR ACTIVE TSSOP PW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74HC273PWT ACTIVE TSSOP PW 20 250 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SNJ54HC273FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54HC273J ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC SNJ54HC273W ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 2
MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96
28 TERMINAL SHOWN
B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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